Philips 8-bit microcontroller with two-clock 80C51 core UM10109 Manual De Usuario
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual
Rev. 02 — 23 May 2005
43 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
control bits ENT0 and ENT1 in the AUXR1 register, and apply to Timer 0 and Timer 1
respectively. The port outputs will be a logic 1 prior to the first timer overflow when this
mode is turned on. In order for this mode to function, the C/T bit must be cleared selecting
PCLK as the clock source for the timer.
respectively. The port outputs will be a logic 1 prior to the first timer overflow when this
mode is turned on. In order for this mode to function, the C/T bit must be cleared selecting
PCLK as the clock source for the timer.
8.
Real-time clock system timer
The P89LPC932A1 has a simple Real-time Clock/System Timer that allows a user to
continue running an accurate timer while the rest of the device is powered down. The
Real-time Clock can be an interrupt or a wake-up source (see
continue running an accurate timer while the rest of the device is powered down. The
Real-time Clock can be an interrupt or a wake-up source (see
The Real-time Clock is a 23-bit down counter. The clock source for this counter can be
either the CPU clock (CCLK) or the XTAL1-2 oscillator, provided that the XTAL1-2
oscillator is not being used as the CPU clock. If the XTAL1-2 oscillator is used as the CPU
clock, then the RTC will use CCLK as its clock source regardless of the state of the
RTCS1:0 in the RTCCON register. There are three SFRs used for the RTC:
either the CPU clock (CCLK) or the XTAL1-2 oscillator, provided that the XTAL1-2
oscillator is not being used as the CPU clock. If the XTAL1-2 oscillator is used as the CPU
clock, then the RTC will use CCLK as its clock source regardless of the state of the
RTCS1:0 in the RTCCON register. There are three SFRs used for the RTC:
RTCCON — Real-time Clock control.
RTCH — Real-time Clock counter reload high (bits 22 to 15).
RTCL — Real-time Clock counter reload low (bits 14 to 7).
The Real-time clock system timer can be enabled by setting the RTCEN (RTCCON.0) bit.
The Real-time Clock is a 23-bit down counter (initialized to all 0’s when RTCEN = 0) that is
comprised of a 7-bit prescaler and a 16-bit loadable down counter. When RTCEN is
written with logic 1, the counter is first loaded with (RTCH, RTCL, ‘1111111’) and will
count down. When it reaches all 0’s, the counter will be reloaded again with (RTCH,
RTCL, ‘1111111’) and a flag - RTCF (RTCCON.7) - will be set.
The Real-time Clock is a 23-bit down counter (initialized to all 0’s when RTCEN = 0) that is
comprised of a 7-bit prescaler and a 16-bit loadable down counter. When RTCEN is
written with logic 1, the counter is first loaded with (RTCH, RTCL, ‘1111111’) and will
count down. When it reaches all 0’s, the counter will be reloaded again with (RTCH,
RTCL, ‘1111111’) and a flag - RTCF (RTCCON.7) - will be set.
Fig 19. Real-time clock/system timer block diagram.
RTCH
RTCL
RTC RESET
power-on
reset
RELOAD ON UNDERFLOW
MSB
LSB
÷128
23-BIT DOWN COUNTER
wake-up from power-down
Interrupt if enabled
(shared with WDT)
(shared with WDT)
002aaa924
ERTC
RTCF
RTC underflow flag
RTCEN
RTC enable
7-BIT PRESCALER
RTCS1 RTCS2
RTC clk select
CCLK
internal
oscillators
LOW FREQUENCY
MEDIUM FREQUENCY
HIGH FREQUENCY
XTAL2
XTAL1