Motorola DSP56012 Manual De Usuario
Serial Host Interface
SHI Programming Considerations
MOTOROLA
DSP56012 User’s Manual
5-23
Note:
The first data byte in a write-bus cycle can be used as a user-predefined
control byte (e.g., to determine the location to which the forthcoming data
bytes should be transferred).
control byte (e.g., to determine the location to which the forthcoming data
bytes should be transferred).
5.7
SHI PROGRAMMING CONSIDERATIONS
The SHI implements both SPI and I
2
C bus protocols and can be programmed to
operate as a slave device or a single-master device. Once the operating mode is
selected, the SHI may communicate with an external device by receiving and/or
transmitting data. Before changing the SHI operational mode, an SHI individual reset
should be generated by clearing the HEN bit. The following paragraphs describe
programming considerations for each operational mode.
selected, the SHI may communicate with an external device by receiving and/or
transmitting data. Before changing the SHI operational mode, an SHI individual reset
should be generated by clearing the HEN bit. The following paragraphs describe
programming considerations for each operational mode.
5.7.1
SPI Slave Mode
The SPI Slave mode is entered by enabling the SHI (HEN = 1), selecting the SPI mode
(HI
(HI
2
C = 0), and selecting the Slave mode of operation (HMST = 0). The programmer
should verify that the CPHA and CPOL bits (in the HCKR) correspond to the
external host clock phase and polarity. Other HCKR bits are ignored. When
configured in the SPI Slave mode, the SHI external pins operate as follows:
external host clock phase and polarity. Other HCKR bits are ignored. When
configured in the SPI Slave mode, the SHI external pins operate as follows:
• SCK/SCL is the SCK serial clock input.
• MISO/SDA is the MISO serial data output.
• MOSI/HA0 is the MOSI serial data input.
• SS/HA2 is the SS Slave Select input.
• HREQ is the Host Request output.
In the SPI Slave mode, a receive, transmit, or full-duplex data transfer may be
performed. Actually, the interface simultaneously performs both data receive and
transmit. The status bits of both receive and transmit paths are active; however, the
programmer may disable undesired interrupts and ignore non-relevant status bits. It
is recommended that an SHI individual reset (HEN cleared) be generated before
beginning data reception in order to reset the HRX FIFO to its initial (empty) state
(e.g., when switching from transmit to receive data).
performed. Actually, the interface simultaneously performs both data receive and
transmit. The status bits of both receive and transmit paths are active; however, the
programmer may disable undesired interrupts and ignore non-relevant status bits. It
is recommended that an SHI individual reset (HEN cleared) be generated before
beginning data reception in order to reset the HRX FIFO to its initial (empty) state
(e.g., when switching from transmit to receive data).
If a write to HTX occurs, its contents are transferred to IOSR between data word
transfers. The IOSR data is shifted out (via MISO) and received data is shifted in (via
MOSI). The DSP may write HTX if the HTDE status bit is set. If no writes to HTX
transfers. The IOSR data is shifted out (via MISO) and received data is shifted in (via
MOSI). The DSP may write HTX if the HTDE status bit is set. If no writes to HTX