Motorola DSP56012 Manual De Usuario

HBIE bit is also set, the SHI issues a request to the DSP interrupt controller to service 
the SHI Bus Error interrupt.

In the SPI Master mode the DSP must write to HTX to receive, transmit, or perform a 
full-duplex data transfer. Actually, the interface performs simultaneous data receive 
and transmit. The status bits of both receive and transmit paths are active; however, 
the programmer may disable undesired interrupts and ignore non-relevant status 
bits. In a data transfer, the HTX is transferred to IOSR, clock pulses are generated, the 
IOSR data is shifted out (via MOSI) and received data is shifted in (via MISO). The 
DSP programmer may write HTX (if the HTDE status bit is set) to initiate the transfer 
of the next word. The HRX FIFO contains valid receive data, which may be read by 
the DSP, if the HRNE status bit is set.

Motorola recommends that an SHI individual reset (HEN cleared) be 
generated before beginning data reception in order to reset the receive FIFO to 
its initial (empty) state, such as when switching from transmit to receive data.

The HREQ input pin is ignored by the SPI master device if the HRQE[1:0] bits are 
cleared, and considered if any of them is set. When asserted by the slave device, 
HREQ indicates that the external slave device is ready for the next data transfer. As a 
result, the SPI master sends clock pulses for the full data word transfer. HREQ is 
deasserted by the external slave device at the first clock pulse of the new data 
transfer. When deasserted, HREQ will prevent the clock generation of the next data 
word transfer until it is asserted again. Connecting the HREQ line between two 
SHI-equipped DSPs, one operating as an SPI master device and the other as an SPI 
slave device, enables full hardware handshaking if CPHA = 1. For CPHA = 0, HREQ 
should be disabled by clearing HRQE[1:0].

The I

2

C Slave mode is entered by enabling the SHI (HEN = 1), selecting the I

2

C mode 

(HI

2

C = 1), and selecting the Slave mode of operation (HMST = 0). In this operational 

mode the contents of HCKR are ignored. When configured in the I

2

C Slave mode, the 

SHI external pins operate as follows:

• SCK/SCL is the SCL serial clock input.

• MISO/SDA is the SDA open drain serial data line.

• MOSI/HA0 is the HA0 slave device address input.

• SS/HA2 is the HA2 slave device address input.

• HREQ is the Host Request output.