Manual De Usuario (BX80569QX6850)Tabla de contenidosContents3Figures5Tables6Revision History7Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Features9Intel® Core™2 Extreme Processor X6800D and Intel® Core™2 Duo Desktop Processor E6000D and E4000D Sequences11 Introduction111.1 Terminology121.1.1 Processor Terminology121.2 References14Table 1. Reference Documents142 Electrical Specifications152.1 Power and Ground Lands152.2 Decoupling Guidelines152.2.1 VCC Decoupling152.2.2 Vtt Decoupling152.2.3 FSB Decoupling162.3 Voltage Identification16Table 2. Voltage Identification Definition172.4 Market Segment Identification (MSID)18Table 3. Market Segment Selection Truth Table for MSID[1:0], , ,182.5 Reserved, Unused, and TESTHI Signals182.6 Voltage and Current Specification192.6.1 Absolute Maximum and Minimum Ratings19Table 4. Absolute Maximum and Minimum Ratings202.6.2 DC Voltage and Current Specification20Table 5. Voltage and Current Specifications20Table 6. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache22Figure 1. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache23Table 7. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache24Figure 2. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache252.6.3 VCC Overshoot25Table 8. VCC Overshoot Specifications25Figure 3. VCC Overshoot Example Waveform262.6.4 Die Voltage Validation262.7 Signaling Specifications262.7.1 FSB Signal Groups27Table 9. FSB Signal Groups27Table 10. Signal Characteristics28Table 11. Signal Reference Voltages282.7.2 CMOS and Open Drain Signals282.7.3 Processor DC Specifications29Table 12. GTL+ Signal Group DC Specifications29Table 13. Open Drain and TAP Output Signal Group DC Specifications29Table 14. CMOS Signal Group DC Specifications302.7.3.1 GTL+ Front Side Bus Specifications30Table 15. GTL+ Bus Voltage Definitions302.7.4 Clock Specifications312.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking31Table 16. Core Frequency to FSB Multiplier Configuration312.7.6 FSB Frequency Select Signals (BSEL[2:0])31Table 17. BSEL[2:0] Frequency Table for BCLK[1:0]322.7.7 Phase Lock Loop (PLL) and Filter322.7.8 BCLK[1:0] Specifications (CK505 based Platforms)32Table 18. Front Side Bus Differential BCLK Specifications32Figure 4. Differential Clock Waveform33Figure 5. Differential Clock Crosspoint Specification33Figure 6. Differential Measurements332.7.9 BCLK[1:0] Specifications (CK410 based Platforms)34Table 19. Front Side Bus Differential BCLK Specifications34Figure 7. Differential Clock Crosspoint Specification342.8 PECI DC Specifications35Table 20. PECI DC Electrical Limits353 Package Mechanical Specifications37Figure 8. Processor Package Assembly Sketch373.1 Package Mechanical Drawing37Figure 9. Processor Package Drawing Sheet 1 of 338Figure 10. Processor Package Drawing Sheet 2 of 339Figure 11. Processor Package Drawing Sheet 3 of 3403.1.1 Processor Component Keep-Out Zones413.1.2 Package Loading Specifications41Table 21. Processor Loading Specifications413.1.3 Package Handling Guidelines41Table 22. Package Handling Guidelines413.1.4 Package Insertion Specifications423.1.5 Processor Mass Specification423.1.6 Processor Materials42Table 23. Processor Materials423.1.7 Processor Markings42Figure 12. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache with 1333 MHz FSB42Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 1066 MHz FSB43Figure 14. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 2 MB L2 Cache43Figure 15. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Sequence with 2 MB L2 Cache44Figure 16. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800443.1.8 Processor Land Coordinates45Figure 17. Processor Land Coordinates and Quadrants (Top View)454 Land Listing and Signal Descriptions474.1 Processor Land Assignments47Figure 18. land-out Diagram (Top View - Left Side)48Figure 19. land-out Diagram (Top View - Right Side)49Table 24. Alphabetical Land Assignments50Table 25. Numerical Land Assignment604.2 Alphabetical Signals Reference70Table 26. Signal Description (Sheet 1 of 9)705 Thermal Specifications and Design Considerations795.1 Processor Thermal Specifications795.1.1 Thermal Specifications79Table 27. Processor Thermal Specifications80Table 28. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache)81Figure 20. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache)81Table 29. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)82Figure 21. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)82Table 30. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)83Figure 22. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)83Table 31. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache)84Figure 23. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache)84Table 32. Thermal Profile (Intel® Core™2 Extreme Processor X6800)85Figure 24. Thermal Profile (Intel® Core™2 Extreme Processor X6800)855.1.2 Thermal Metrology86Figure 25. Case Temperature (TC) Measurement Location865.2 Processor Thermal Features865.2.1 Thermal Monitor865.2.2 Thermal Monitor 287Figure 26. Thermal Monitor 2 Frequency and Voltage Ordering885.2.3 On-Demand Mode885.2.4 PROCHOT# Signal895.2.5 THERMTRIP# Signal895.3 Thermal Diode90Table 33. Thermal “Diode” Parameters using Diode Model90Table 34. Thermal “Diode” Parameters using Transistor Model91Table 35. Thermal Diode Interface915.4 Platform Environment Control Interface (PECI)925.4.1 Introduction92Figure 27. Processor PECI Topology925.4.1.1 Key Difference with Legacy Diode-Based Thermal Management92Figure 28. Conceptual Fan Control on PECI-Based Platforms93Figure 29. Conceptual Fan Control on Thermal Diode-Based Platforms935.4.2 PECI Specifications945.4.2.1 PECI Device Address945.4.2.2 PECI Command Support945.4.2.3 PECI Fault Handling Requirements945.4.2.4 PECI GetTemp0() Error Code Support94Table 36. GetTemp0() Error Codes946 Features956.1 Power-On Configuration Options95Table 37. Power-On Configuration Option Signals956.2 Clock Control and Low Power States95Figure 30. Processor Low Power State Machine966.2.1 Normal State966.2.2 HALT and Extended HALT Powerdown States966.2.2.1 HALT Powerdown State966.2.2.2 Extended HALT Powerdown State976.2.3 Stop Grant and Extended Stop Grant States976.2.3.1 Stop Grant State976.2.3.2 Extended Stop Grant State986.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State986.2.4.1 HALT Snoop State, Stop Grant Snoop State986.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State986.3 Enhanced Intel® SpeedStep® Technology987 Boxed Processor Specifications101Figure 31. Mechanical Representation of the Boxed Processor1017.1 Mechanical Specifications1027.1.1 Boxed Processor Cooling Solution Dimensions102Figure 32. Space Requirements for the Boxed Processor (Side View)102Figure 33. Space Requirements for the Boxed Processor (Top View)102Figure 34. Space Requirements for the Boxed Processor (Overall View)1037.1.2 Boxed Processor Fan Heatsink Weight1037.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly1037.2 Electrical Requirements1037.2.1 Fan Heatsink Power Supply103Figure 35. Boxed Processor Fan Heatsink Power Cable Connector Description104Table 38. Fan Heatsink Power and Signal Specifications104Figure 36. Baseboard Power Header Placement Relative to Processor Socket1057.3 Thermal Specifications1057.3.1 Boxed Processor Cooling Requirements105Figure 37. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)106Figure 38. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)1067.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only)1077.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences Only)107Figure 39. Boxed Processor Fan Heatsink Set Points108Table 39. Fan Heatsink Power and Signal Specifications1088 Balanced Technology Extended (BTX) Boxed Processor Specifications111Figure 40. Mechanical Representation of the Boxed Processor with a Type I TMA111Figure 41. Mechanical Representation of the Boxed Processor with a Type II TMA1128.1 Mechanical Specifications1128.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions112Figure 42. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes113Figure 43. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume1148.1.2 Boxed Processor Thermal Module Assembly Weight1148.1.3 Boxed Processor Support and Retention Module (SRM)115Figure 44. Assembly Stack Including the Support and Retention Module1158.2 Electrical Requirements1168.2.1 Thermal Module Assembly Power Supply116Figure 45. Boxed Processor TMA Power Cable Connector Description116Table 40. TMA Power and Signal Specifications117Figure 46. Balanced Technology Extended (BTX) Mainboard Power Header Placement (hatched area)1178.3 Thermal Specifications1188.3.1 Boxed Processor Cooling Requirements1188.3.2 Variable Speed Fan118Figure 47. Boxed Processor TMA Set Points119Table 41. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors1199 Debug Tools Specifications1219.1 Logic Analyzer Interface (LAI)1219.1.1 Mechanical Considerations1219.1.2 Electrical Considerations121Tamaño: 2 MBPáginas: 122Language: EnglishManuales abiertas