Manuais de utilizador para Intel Core 2 Extreme QX6850

índice analítico

• Contents

  3
  • Figures

    5
  • Tables

    6
• Revision History

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• Intel® Core™2 Extreme Processor X6800 and Intel® Core™2 Duo Desktop Processor E6000 and E4000 Sequence Features

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• Intel® Core™2 Extreme Processor X6800D and Intel® Core™2 Duo Desktop Processor E6000D and E4000D Sequences

  1
• 1 Introduction

  11
  • 1.1 Terminology

    12
    • 1.1.1 Processor Terminology

      12
  • 1.2 References

    14
    • Table 1. Reference Documents

      14
• 2 Electrical Specifications

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  • 2.1 Power and Ground Lands

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  • 2.2 Decoupling Guidelines

    15
    • 2.2.1 VCC Decoupling

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    • 2.2.2 Vtt Decoupling

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    • 2.2.3 FSB Decoupling

      16
  • 2.3 Voltage Identification

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    • Table 2. Voltage Identification Definition

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  • 2.4 Market Segment Identification (MSID)

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    • Table 3. Market Segment Selection Truth Table for MSID[1:0], , ,

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  • 2.5 Reserved, Unused, and TESTHI Signals

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  • 2.6 Voltage and Current Specification

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    • 2.6.1 Absolute Maximum and Minimum Ratings

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      • Table 4. Absolute Maximum and Minimum Ratings

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    • 2.6.2 DC Voltage and Current Specification

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      • Table 5. Voltage and Current Specifications

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      • Table 6. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache

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      • Figure 1. VCC Static and Transient Tolerance for Processors with 4 MB L2 Cache

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      • Table 7. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache

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      • Figure 2. VCC Static and Transient Tolerance for Processors with 2 MB L2 Cache

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    • 2.6.3 VCC Overshoot

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      • Table 8. VCC Overshoot Specifications

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      • Figure 3. VCC Overshoot Example Waveform

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    • 2.6.4 Die Voltage Validation

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  • 2.7 Signaling Specifications

    26
    • 2.7.1 FSB Signal Groups

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      • Table 9. FSB Signal Groups

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      • Table 10. Signal Characteristics

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      • Table 11. Signal Reference Voltages

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    • 2.7.2 CMOS and Open Drain Signals

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    • 2.7.3 Processor DC Specifications

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      • Table 12. GTL+ Signal Group DC Specifications

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      • Table 13. Open Drain and TAP Output Signal Group DC Specifications

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      • Table 14. CMOS Signal Group DC Specifications

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      • 2.7.3.1 GTL+ Front Side Bus Specifications

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        • Table 15. GTL+ Bus Voltage Definitions

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    • 2.7.4 Clock Specifications

      31
    • 2.7.5 Front Side Bus Clock (BCLK[1:0]) and Processor Clocking

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      • Table 16. Core Frequency to FSB Multiplier Configuration

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    • 2.7.6 FSB Frequency Select Signals (BSEL[2:0])

      31
      • Table 17. BSEL[2:0] Frequency Table for BCLK[1:0]

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    • 2.7.7 Phase Lock Loop (PLL) and Filter

      32
    • 2.7.8 BCLK[1:0] Specifications (CK505 based Platforms)

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      • Table 18. Front Side Bus Differential BCLK Specifications

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      • Figure 4. Differential Clock Waveform

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      • Figure 5. Differential Clock Crosspoint Specification

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      • Figure 6. Differential Measurements

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    • 2.7.9 BCLK[1:0] Specifications (CK410 based Platforms)

      34
      • Table 19. Front Side Bus Differential BCLK Specifications

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      • Figure 7. Differential Clock Crosspoint Specification

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  • 2.8 PECI DC Specifications

    35
    • Table 20. PECI DC Electrical Limits

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• 3 Package Mechanical Specifications

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  • Figure 8. Processor Package Assembly Sketch

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  • 3.1 Package Mechanical Drawing

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    • Figure 9. Processor Package Drawing Sheet 1 of 3

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    • Figure 10. Processor Package Drawing Sheet 2 of 3

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    • Figure 11. Processor Package Drawing Sheet 3 of 3

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    • 3.1.1 Processor Component Keep-Out Zones

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    • 3.1.2 Package Loading Specifications

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      • Table 21. Processor Loading Specifications

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    • 3.1.3 Package Handling Guidelines

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      • Table 22. Package Handling Guidelines

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    • 3.1.4 Package Insertion Specifications

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    • 3.1.5 Processor Mass Specification

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    • 3.1.6 Processor Materials

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      • Table 23. Processor Materials

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    • 3.1.7 Processor Markings

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      • Figure 12. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache with 1333 MHz FSB

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      • Figure 13. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 4 MB L2 Cache with 1066 MHz FSB

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      • Figure 14. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E6000 Sequence with 2 MB L2 Cache

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      • Figure 15. Processor Top-Side Markings Example for the Intel® Core™2 Duo Desktop Processors E4000 Sequence with 2 MB L2 Cache

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      • Figure 16. Processor Top-Side Markings for the Intel® Core™2 Extreme Processor X6800

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    • 3.1.8 Processor Land Coordinates

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      • Figure 17. Processor Land Coordinates and Quadrants (Top View)

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• 4 Land Listing and Signal Descriptions

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  • 4.1 Processor Land Assignments

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    • Figure 18. land-out Diagram (Top View - Left Side)

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    • Figure 19. land-out Diagram (Top View - Right Side)

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    • Table 24. Alphabetical Land Assignments

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    • Table 25. Numerical Land Assignment

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  • 4.2 Alphabetical Signals Reference

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    • Table 26. Signal Description (Sheet 1 of 9)

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• 5 Thermal Specifications and Design Considerations

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  • 5.1 Processor Thermal Specifications

    79
    • 5.1.1 Thermal Specifications

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      • Table 27. Processor Thermal Specifications

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      • Table 28. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache)

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      • Figure 20. Thermal Profile (Intel® Core™2 Duo Desktop Processor E6x50 Sequence and E6540 with 4 MB L2 Cache)

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      • Table 29. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)

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      • Figure 21. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 Sequence with 4 MB L2 Cache)

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      • Table 30. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)

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      • Figure 22. Thermal Profile (Intel® Core™2 Duo Desktop Processor E4500 and E4600 with 2 MB L2 Cache)

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      • Table 31. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache)

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      • Figure 23. Thermal Profile (Intel® Core™ Duo Desktop Processor E6000 and E4000 Sequence with 2 MB L2 Cache)

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      • Table 32. Thermal Profile (Intel® Core™2 Extreme Processor X6800)

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      • Figure 24. Thermal Profile (Intel® Core™2 Extreme Processor X6800)

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    • 5.1.2 Thermal Metrology

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      • Figure 25. Case Temperature (TC) Measurement Location

        86
  • 5.2 Processor Thermal Features

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    • 5.2.1 Thermal Monitor

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    • 5.2.2 Thermal Monitor 2

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      • Figure 26. Thermal Monitor 2 Frequency and Voltage Ordering

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    • 5.2.3 On-Demand Mode

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    • 5.2.4 PROCHOT# Signal

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    • 5.2.5 THERMTRIP# Signal

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  • 5.3 Thermal Diode

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    • Table 33. Thermal “Diode” Parameters using Diode Model

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    • Table 34. Thermal “Diode” Parameters using Transistor Model

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    • Table 35. Thermal Diode Interface

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  • 5.4 Platform Environment Control Interface (PECI)

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    • 5.4.1 Introduction

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      • Figure 27. Processor PECI Topology

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      • 5.4.1.1 Key Difference with Legacy Diode-Based Thermal Management

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        • Figure 28. Conceptual Fan Control on PECI-Based Platforms

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        • Figure 29. Conceptual Fan Control on Thermal Diode-Based Platforms

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    • 5.4.2 PECI Specifications

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      • 5.4.2.1 PECI Device Address

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      • 5.4.2.2 PECI Command Support

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      • 5.4.2.3 PECI Fault Handling Requirements

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      • 5.4.2.4 PECI GetTemp0() Error Code Support

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        • Table 36. GetTemp0() Error Codes

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• 6 Features

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  • 6.1 Power-On Configuration Options

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    • Table 37. Power-On Configuration Option Signals

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  • 6.2 Clock Control and Low Power States

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    • Figure 30. Processor Low Power State Machine

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    • 6.2.1 Normal State

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    • 6.2.2 HALT and Extended HALT Powerdown States

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      • 6.2.2.1 HALT Powerdown State

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      • 6.2.2.2 Extended HALT Powerdown State

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    • 6.2.3 Stop Grant and Extended Stop Grant States

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      • 6.2.3.1 Stop Grant State

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      • 6.2.3.2 Extended Stop Grant State

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    • 6.2.4 Extended HALT State, HALT Snoop State, Extended Stop Grant Snoop State, and Stop Grant Snoop State

      98
      • 6.2.4.1 HALT Snoop State, Stop Grant Snoop State

        98
      • 6.2.4.2 Extended HALT Snoop State, Extended Stop Grant Snoop State

        98
  • 6.3 Enhanced Intel® SpeedStep® Technology

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• 7 Boxed Processor Specifications

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  • Figure 31. Mechanical Representation of the Boxed Processor

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  • 7.1 Mechanical Specifications

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    • 7.1.1 Boxed Processor Cooling Solution Dimensions

      102
      • Figure 32. Space Requirements for the Boxed Processor (Side View)

        102
      • Figure 33. Space Requirements for the Boxed Processor (Top View)

        102
      • Figure 34. Space Requirements for the Boxed Processor (Overall View)

        103
    • 7.1.2 Boxed Processor Fan Heatsink Weight

      103
    • 7.1.3 Boxed Processor Retention Mechanism and Heatsink Attach Clip Assembly

      103
  • 7.2 Electrical Requirements

    103
    • 7.2.1 Fan Heatsink Power Supply

      103
      • Figure 35. Boxed Processor Fan Heatsink Power Cable Connector Description

        104
      • Table 38. Fan Heatsink Power and Signal Specifications

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      • Figure 36. Baseboard Power Header Placement Relative to Processor Socket

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  • 7.3 Thermal Specifications

    105
    • 7.3.1 Boxed Processor Cooling Requirements

      105
      • Figure 37. Boxed Processor Fan Heatsink Airspace Keepout Requirements (side 1 view)

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      • Figure 38. Boxed Processor Fan Heatsink Airspace Keepout Requirements (Side 2 View)

        106
    • 7.3.2 Fan Speed Control Operation (Intel® Core2 Extreme Processor X6800 Only)

      107
    • 7.3.3 Fan Speed Control Operation (Intel® Core2 Duo Desktop Processor E6000 and E4000 Sequences Only)

      107
      • Figure 39. Boxed Processor Fan Heatsink Set Points

        108
      • Table 39. Fan Heatsink Power and Signal Specifications

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• 8 Balanced Technology Extended (BTX) Boxed Processor Specifications

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  • Figure 40. Mechanical Representation of the Boxed Processor with a Type I TMA

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  • Figure 41. Mechanical Representation of the Boxed Processor with a Type II TMA

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  • 8.1 Mechanical Specifications

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    • 8.1.1 Balanced Technology Extended (BTX) Type I and Type II Boxed Processor Cooling Solution Dimensions

      112
      • Figure 42. Requirements for the Balanced Technology Extended (BTX) Type I Keep-out Volumes

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      • Figure 43. Requirements for the Balanced Technology Extended (BTX) Type II Keep-out Volume

        114
    • 8.1.2 Boxed Processor Thermal Module Assembly Weight

      114
    • 8.1.3 Boxed Processor Support and Retention Module (SRM)

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      • Figure 44. Assembly Stack Including the Support and Retention Module

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  • 8.2 Electrical Requirements

    116
    • 8.2.1 Thermal Module Assembly Power Supply

      116
      • Figure 45. Boxed Processor TMA Power Cable Connector Description

        116
      • Table 40. TMA Power and Signal Specifications

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      • Figure 46. Balanced Technology Extended (BTX) Mainboard Power Header Placement (hatched area)

        117
  • 8.3 Thermal Specifications

    118
    • 8.3.1 Boxed Processor Cooling Requirements

      118
    • 8.3.2 Variable Speed Fan

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      • Figure 47. Boxed Processor TMA Set Points

        119
      • Table 41. TMA Set Points for 3-wire operation of BTX Type I and Type II Boxed Processors

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• 9 Debug Tools Specifications

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  • 9.1 Logic Analyzer Interface (LAI)

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    • 9.1.1 Mechanical Considerations

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    • 9.1.2 Electrical Considerations

      121