Manual De UsuarioTabla de contenidosChapter1 General Description131.1 TolerANT® Technology141.2 LSI53C810A Benefits Summary151.2.1 SCSI Performance151.2.2 PCI Performance161.2.3 Integration161.2.4 Ease of Use161.2.5 Flexibility171.2.6 Reliability171.2.7 Testability18Figure1.1 LSI53C810A System Diagram19Figure1.2 LSI53C810A Chip Block Diagram20Chapter2 Functional Description212.1 SCSI Core212.1.1 DMA Core222.2 SCRIPTS Processor222.2.1 SDMS Software: The Total SCSI Solution232.3 Prefetching SCRIPTS Instructions232.3.1 Opcode Fetch Burst Capability242.4 PCI Cache Mode242.4.1 Load and Store Instructions252.4.2 3.3 V/5 V PCI Interface252.4.3 Loopback Mode252.5 Parity Options25Table 2.1 Bits Used for Parity Control and Observation26Table 2.2 SCSI Parity Control27Table 2.3 SCSI Parity Errors and Interrupts272.5.1 DMA FIFO28Figure2.1 DMA FIFO Sections282.5.1.1 Data Paths28Figure2.2 LSI53C810A Host Interface Data Paths302.6 SCSI Bus Interface312.6.1 Terminator Networks312.6.2 Select/Reselect During Selection/Reselection31Figure2.3 Active or Regulated Termination322.6.3 Synchronous Operation332.6.3.1 Determining the Data Transfer Rate332.6.3.2 SCNTL3 Register, Bits [6:4] (SCF[2:0])332.6.3.3 SCNTL3 Register, Bits [2:0] (CCF[2:0])342.6.3.4 SXFER Register, Bits [7:5] (TP[2:0])342.6.3.5 Achieving Optimal SCSI Send Rates34Figure2.4 Determining the Synchronous Transfer Rate352.7 Interrupt Handling352.7.1 Polling and Hardware Interrupts352.7.1.1 Registers362.7.1.2 Fatal vs. Nonfatal Interrupts382.7.1.3 Masking382.7.1.4 Stacked Interrupts392.7.1.5 Halting in an Orderly Fashion402.7.1.6 Sample Interrupt Service Routine41Chapter3 PCI Functional Description433.1 PCI Addressing433.1.1 Configuration Space433.1.2 PCI Bus Commands and Functions Supported443.1.2.1 I/O Read Command443.1.2.2 I/O Write Command443.1.2.3 Memory Read Command453.1.2.4 Memory Read Multiple Command453.1.2.5 Memory Read Line Command453.1.2.6 Memory Write Command453.1.2.7 Memory Write and Invalidate Command453.2 PCI Cache Mode453.2.1 Support for PCI Cache Line Size Register453.2.2 Selection of Cache Line Size463.2.3 Alignment463.2.3.1 MMOV Misalignment463.2.3.2 Memory Write and Invalidate Command473.2.3.3 Memory Read Line Command483.2.4 Memory Read Multiple Command493.2.5 Unsupported PCI Commands50Table 3.1 PCI Bus Commands and Encoding Types513.3 Configuration Registers51Table 3.2 PCI Configuration Register Map52Chapter4 Signal Descriptions63Figure4.1 LSI53C810A Pin Diagram64Table 4.1 Power and Ground Signals65Figure4.2 Functional Signal Grouping664.1 PCI Bus Interface Signals674.1.1 System Signals67Table 4.2 System Signals674.1.2 Address and Data Signals68Table 4.3 Address and Data Signals684.1.3 Interface Control Signals69Table 4.4 Interface Control Signals694.1.4 Arbitration Signals70Table 4.5 Arbitration Signals704.1.5 Error Reporting Signals70Table 4.6 Error Reporting Signals704.2 SCSI Bus Interface Signals714.2.1 SCSI Bus Interface Signals71Table 4.7 SCSI Bus Interface Signals714.2.2 Additional Interface Signals72Table 4.8 Additional Interface Signals72Chapter5 Operating Registers75Figure5.1 Register Address Map76Table 5.1 Synchronous Clock Conversion Factor84Table 5.2 Asynchronous Clock Conversion Factor85Table 5.3 Examples of Synchronous Transfer Periods and Rates for SCSI-187Table 5.4 Examples of Synchronous Transfer Periods and Rates for Fast SCSI88Table 5.5 SCSI Synchronous Offset Values89Chapter6 Instruction Set of the I/O Processor1416.1 Low Level Register Interface Mode1416.2 SCSI SCRIPTS142Table 6.1 SCRIPTS Instructions1436.2.1 Sample Operation143Figure6.1 SCRIPTS Overview1456.3 Block Move Instructions1456.3.1 First Dword146Figure6.2 Block Move Instruction Register1486.3.2 Second Dword1526.4 I/O Instruction1536.4.1 First Dword153Figure6.3 I/O Instruction Register1566.4.2 Second Dword1626.5 Read/Write Instructions1636.5.1 First Dword1636.5.2 Second Dword1636.5.3 Read-Modify-Write Cycles1636.5.4 Move To/From SFBR Cycles164Figure6.4 Read/Write Register Instruction165Table 6.2 Read/Write Instructions1666.6 Transfer Control Instructions1676.6.1 First Dword167Figure6.5 Transfer Control Instruction1706.6.2 Second Dword1756.7 Memory Move Instructions176Figure6.6 Memory to Memory Move Instruction1776.7.1 First Dword1786.7.2 Second Dword1786.7.3 Third Dword1786.7.4 Read/Write System Memory from a SCRIPTS Instruction1796.8 Load and Store Instructions1796.8.1 First Dword1806.8.2 Second Dword181Figure6.7 Load and Store Instruction Format182Chapter7 Electrical Characteristics1837.1 DC Characteristics183Table 7.1 Absolute Maximum Stress Ratings184Table 7.2 Operating Conditions184Table 7.3 SCSI Signals—SD[7:0]/, SDP/, SREQ/, SACK/185Table 7.4 SCSI Signals—SMSG, SI_O/, SC_D/, SATN/, SBSY/, SSEL/, SRST/185Table 7.5 Input Signals—CLK, SCLK, GNT/, IDSEL, RST/, TESTIN185Table 7.6 Capacitance186Table 7.7 Output Signals—MAC/_TESTOUT, REQ/186Table 7.8 Output Signal—IRQ/186Table 7.9 Output Signal—SERR/187Table 7.10 Bidirectional Signals—AD[31:0], C_BE/[3:0], FRAME/, IRDY/, TRDY/, DEVSEL/, STOP/, PERR...187Table 7.11 Bidirectional Signals—GPIO0_FETCH/, GPIO1_MASTER/1887.2 TolerANT Technology188Table 7.12 TolerANT Technology Electrical Characteristics189Figure7.1 Rise and Fall Time Test Conditions190Figure7.2 SCSI Input Filtering190Figure7.3 Hysteresis of SCSI Receiver190Figure7.4 Input Current as a Function of Input Voltage191Figure7.5 Output Current as a Function of Output Voltage1917.3 AC Characteristics192Table 7.13 Clock Timing192Figure7.6 Clock Timing192Table 7.14 Reset Input Timing193Figure7.7 Reset Input193Table 7.15 Interrupt Output193Figure7.8 Interrupt Output Waveforms1937.4 PCI Interface Timing Diagrams1947.4.1 Target Timing195Figure7.9 PCI Configuration Register Read195Figure7.10 PCI Configuration Register Write196Figure7.11 Target Read197Figure7.12 Target Write1987.4.2 Initiator Timing199Figure7.13 OpCode Fetch, Nonburst199Figure7.14 Burst Opcode Fetch200Figure7.15 Back-to-Back Read201Figure7.16 Back-to-Back Write202Figure7.17 Burst Read204Figure7.18 Burst Write2067.5 PCI Interface Timing208Table 7.16 PCI Timing2087.6 SCSI Timings209Table 7.17 Initiator Asynchronous Send (5 Mbytes/s)209Figure7.19 Initiator Asynchronous Send209Table 7.18 Initiator Asynchronous Receive (5 Mbytes/s)210Figure7.20 Initiator Asynchronous Receive210Table 7.19 Target Asynchronous Send (5 Mbytes/s)211Figure7.21 Target Asynchronous Send211Table 7.20 Target Asynchronous Receive (5 Mbytes/s)212Figure7.22 Target Asynchronous Receive212Figure7.23 Initiator and Target Synchronous Transfers212Table 7.21 SCSI-1 Transfers (SE, 5.0 Mbytes/s)213Table 7.22 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 40 MHz Clock)213Table 7.23 SCSI-2 Fast Transfers (10.0 Mbytes/s (8-Bit Transfers), 50 MHz Clock)2147.7 Package Drawings215Figure7.24 100 LD PQFP (UD) Mechanical Drawing (Sheet 1 of 2)216AppendixA Register Summary219TableA.1 Configuration Registers219TableA.2 SCSI Registers220Index223Customer Feedback231Tamaño: 1000 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