Emerson 752I Manuel D’Utilisation
System Controller:
Doorbell Registers
5-6
monitor the state of the PCI bus INTA*—INTD* signals (PCI1 only). The MV64460 contains
registers that control the masking, unmasking, and priority of the PMC interrupts as inputs
to the processor.
registers that control the masking, unmasking, and priority of the PMC interrupts as inputs
to the processor.
DOORBELL REGISTERS
The MV64460 uses the doorbell registers in the messaging unit (MU) to request interrupts
on both the PCI and CPU buses. There are two types of doorbell registers:
on both the PCI and CPU buses. There are two types of doorbell registers:
Outbound:
These are set by the MV64460’s local CPU to request an interrupt service on the PCI bus.
Inbound:
These are set by an external PCI agent to request interrupt service from the local CPU.
Outbound Doorbells
The local CPU generates an interrupt request to the PCI bus by setting bits in the Outbound
Doorbell register (ODR). The interrupt may be masked in the Outbound Interrupt Mask reg-
ister (OIMR), but that does not prevent the bit from being set in the ODR. The ODR is
located at PCI_0 offset 0x1C2C.
Doorbell register (ODR). The interrupt may be masked in the Outbound Interrupt Mask reg-
ister (OIMR), but that does not prevent the bit from being set in the ODR. The ODR is
located at PCI_0 offset 0x1C2C.
Note:
The CPU or the PCI interface can set the ODR bits. This allows for passing interrupt requests between CPU and
PCI interfaces.
PCI interfaces.
Inbound Doorbells
The PCI bus generates an interrupt request to the local CPU by setting bits in the Inbound
Doorbell register (IDR). The interrupt may be masked in the Inbound Interrupt Mask regis-
ter (IIMR), but masking the interrupt does not prevent the bit from being set in the IDR. The
IDR is located at PCI_0 offset 0x1C20.
Doorbell register (IDR). The interrupt may be masked in the Inbound Interrupt Mask regis-
ter (IIMR), but masking the interrupt does not prevent the bit from being set in the IDR. The
IDR is located at PCI_0 offset 0x1C20.
Note:
The interrupt request triggered from the PCI bus can be targeted to the CPU or to the PCI interface, depending
on the software setting of the interrupt mask registers.
on the software setting of the interrupt mask registers.
WATCHDOG TIMER
The 32-bit count down watchdog timer generates a nonmaskable interrupt or resets the
system in the event of unpredictable software behavior. After the watchdog is enabled, it is
a free-running counter that requires periodic servicing to prevent its expiration. After reset,
the watchdog is disabled.
system in the event of unpredictable software behavior. After the watchdog is enabled, it is
a free-running counter that requires periodic servicing to prevent its expiration. After reset,
the watchdog is disabled.
RESET
Circuitry on the Katana
752i resets the entire board if the voltages fall out of tolerance or if
the optional on-board reset switch is activated. Please refer to Chapter for additional infor-
mation.
mation.