Emerson 752I Manuel D’Utilisation
System Controller:
On-Card Memory
5-7
ON-CARD MEMORY
The Katana
752i has various types of on-card memory to support the MV64460 system
controller and the 750GL processor. It has user Flash, SDRAM for data storage, and several
serial EEPROMs for non-volatile memory storage. The following subsections describe these
memory devices.
serial EEPROMs for non-volatile memory storage. The following subsections describe these
memory devices.
User Flash
The Katana
752i user Flash memory interface supports soldered devices of 32, 64, or 128
megabytes for the processor complex. The 32-megabyte configuration uses one bank of
two 128 Mbit devices. The 64-megabyte configuration uses two banks of two 128 Mbit
devices or one bank of 256 Mbit devices. The 128-megabyte configuration uses two banks
of two 256 megabit devices. The soldered Flash banks provide a maximum of 128 mega-
bytes of contiguous true Flash file system (TFFS) memory. The MV64460 controls this
memory, located at E800,0000
two 128 Mbit devices. The 64-megabyte configuration uses two banks of two 128 Mbit
devices or one bank of 256 Mbit devices. The 128-megabyte configuration uses two banks
of two 256 megabit devices. The soldered Flash banks provide a maximum of 128 mega-
bytes of contiguous true Flash file system (TFFS) memory. The MV64460 controls this
memory, located at E800,0000
16
on the processor 60x bus. By default, the 750GL proces-
sor boots from the soldered Flash (see Jumper JP2 location on page 2-5).
In addition to the soldered Flash memory, the Katana
752i also supports a single Flash
memory device of up to 512 kilobytes for the 750GL processor complex. This memory
device is socketed and located at F800,0000
device is socketed and located at F800,0000
16
on the processor 60x bus. The 750GL pro-
cessor can write to and boot from this memory.
SDRAM
The Katana
752i supports up to two gigabytes of 72-bit wide synchronous dynamic ran-
dom access memory (SDRAM) for the 750GL processor complex. The SDRAM interface
implements eight additional bits to allow for error correcting code (ECC).
implements eight additional bits to allow for error correcting code (ECC).
Note:
If a standard two-gigabyte SO-DIMM is installed, PMC Site #1 becomes inaccessible due to the dimensions of
the SO-DIMM. Also, the CPU and local bus frequencies are slightly different for this configuration. Using a
two-gigabyte SO-DIMM will slightly increase the Katana
the SO-DIMM. Also, the CPU and local bus frequencies are slightly different for this configuration. Using a
two-gigabyte SO-DIMM will slightly increase the Katana
752i’s airflow requirements.
The SDRAM is in the form of a small-outline, dual in-line memory module (SO-DIMM)
device. A serial EEPROM on the SO-DIMM provides configuration information, accessible via
the I
device. A serial EEPROM on the SO-DIMM provides configuration information, accessible via
the I
2
C interface at address AE
16
. The SDRAM occupies physical addresses from
0000,0000
16
to 7FFF,FFFF
16
on the processor 60x bus. The MV64460 controls the SDRAM
and supports a double data rate (DDR) interface that allows for transfer speeds of up to 400
MHz (clock rates of up to 200 MHz).
MHz (clock rates of up to 200 MHz).