Nxp Semiconductors UM10310 Manuel D’Utilisation

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UM10

310_

1

©

 NXP

 B.V

. 2008.

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[1]

Extended SFRs are physically located on-chip but logically located in external data memory address space (XDATA). The MOVX A,@DPTR and MOVX @DPTR,A instructions are 
used to access these extended SFRs.

[2]

The BOICFG1/0 will be copied from UCFG1.5 and UCFG1.3 when power-on reset.

[3]

CLKCON register reset value comes from UCFG1 and UCFG2. The reset value of CLKCON.2 to CLKCON.0 come from UCFG1.2 to UCFG1.0 and reset value of CLKDBL bit 
comes from UCFG2.7.

[4]

On power-on reset and watchdog reset, the PGAxTRIM8X16X and PGAxTRIM2X4X registers are initialized with a factory preprogrammed value. Other resets will not cause 
initialization.

BODCFG

BOD 
configuration 
register

FFC8H

-

-

-

-

-

-

BOICFG1 BOICFG0

CLKCON

CLOCK Control 
register

FFDEH

CLKOK

-

-

XTALWD

CLKDBL

FOSC2

FOSC1

FOSC0

1000 0100

PGACON1

PGA1 control 
register

FFE1H

ENPGA1

PGASEL1

1

PGASEL1

0

PGATRIM

1

-

-

PGAG11

PGAG10 00

0000 0000

PGACON1B

PGA1 control 
register B

FFE4H

-

-

-

-

-

-

-

PGAENO

FF1

00

0000 0000

PGA1TRIM8X16X PGA1 trim 

register

FFE3H 16XTRIM3 16XTRIM2 16XTRIM1 16XTRIM0 8XTRIM3 8XTRIM2 8XTRIM1

8XTRIM0

PGA1TRIM2X4X

PGA1 trim 
register

FFE2H

4XTRIM3

4XTRIM2

4XTRIM1

4XTRIM0

2XTRIM3 2XTRIM2 2XTRIM1

2XTRIM0

RTCDATH

Real-time clock 
data register 
high

FFBFH

00

0000 0000

RTCDATL

Real-time clock 
data register low

FFBEH

00

0000 0000