Nxp Semiconductors UM10310 Manuel D’Utilisation

UM10310_1

© NXP B.V. 2008. All rights reserved.

 

The P89LPC9321 uses an enhanced 80C51 CPU which runs at six times the speed of 
standard 80C51 devices. A machine cycle consists of two CPU clock cycles, and most 
instructions execute in one or two machine cycles.

The P89LPC9321 device has several internal clocks as defined below:

OSCCLK — Input to the DIVM clock divider. OSCCLK is selected from one of four clock 
sources and can also be optionally divided to a slower frequency (see 

 and 

). Note: f

osc

 is defined as 

the OSCCLK frequency.

CCLK — CPU clock; output of the DIVM clock divider. There are two CCLK cycles per 
machine cycle, and most instructions are executed in one to two machine cycles (two or 
four CCLK cycles).

RCCLK — The internal 7.373 MHz RC oscillator output.The clock doubler option, when 
enabled, provides an output frequency of 14.746 MHz.

PCLK — Clock for the various peripheral devices and is 

CCLK

⁄

2

.

The P89LPC9351 provides several user-selectable oscillator options in generating the 
CPU clock. This allows optimization for a range of needs from high precision to lowest 
possible cost. These options are configured when the flash is programmed and include an 
on-chip watchdog oscillator, an on-chip RC oscillator, an oscillator using an external 
crystal, or an external clock source. 

The external crystal oscillator can be optimized for low, medium, or high frequency 
crystals covering a range from 20 kHz to 18 MHz. It can be the clock source of OSCCLK, 
RTC and WDT.

This option supports an external crystal in the range of 20 kHz to 100 kHz. Ceramic 
resonators are also supported in this configuration

DATA

Directly and indirectly addressable memory

128

IDATA

Indirectly addressable memory

256

XDATA

Auxiliary (‘External Data’) on-chip memory that is accessed using 
the MOVX instructions

512