Nxp Semiconductors UM10310 Manuel D’Utilisation

UM10310_1

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3

IE1

Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware 
when the interrupt is processed, or by software.

4

TR0

Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.

5

TF0

Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the 
processor vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware)

6

TR1

Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off

7

TF1

Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt 
is processed, or by software (except in mode 6, see above, when it is cleared in hardware).