IBM powerpc 750gx Manuel D’Utilisation
User’s Manual
IBM PowerPC 750GX and GL RISC Microprocessor
Exceptions
Page 164 of 377
gx_04.fm.(1.2)
March 27, 2006
4.5.1.1 Soft Reset
If SRESET is asserted, the processor is first put in a recoverable state. To do this, the 750GX allows any
instruction at the point of completion to either complete or take an exception, blocks completion of any subse-
quent instructions, and allows the completion queue to drain. The state before the exception occurred is then
saved as specified in the PowerPC Architecture, and instruction fetching begins at the system reset interrupt
vector offset, 0x00100. The vector address on a soft reset depends on the setting of MSR[IP] (either
0x0000_0100 or 0xFFF0_0100). Soft resets are third in priority, after hard resets and machine checks. This
exception is recoverable provided attaining a recoverable state does not generate a machine check.
instruction at the point of completion to either complete or take an exception, blocks completion of any subse-
quent instructions, and allows the completion queue to drain. The state before the exception occurred is then
saved as specified in the PowerPC Architecture, and instruction fetching begins at the system reset interrupt
vector offset, 0x00100. The vector address on a soft reset depends on the setting of MSR[IP] (either
0x0000_0100 or 0xFFF0_0100). Soft resets are third in priority, after hard resets and machine checks. This
exception is recoverable provided attaining a recoverable state does not generate a machine check.
SRESET is an effectively edge-sensitive signal that can be asserted and deasserted asynchronously,
provided the minimum pulse width specified in the PowerPC 750GX RISC Microprocessor Datasheet is met.
Asserting SRESET causes the 750GX to take a system reset exception. This exception modifies the MSR,
SRR0, and SRR1, as described in the PowerPC Microprocessor Family: The Programming Environments
Manual. Unlike a hard reset, a soft reset does not directly affect the states of output signals. Attempts to use
SRESET during a hard reset sequence or while the Joint Test Action Group (JTAG) logic is non-idle cause
unpredictable results (see Section 7.2.10.2, Soft Reset (SRESET)—Input, on page 272 for more information).
provided the minimum pulse width specified in the PowerPC 750GX RISC Microprocessor Datasheet is met.
Asserting SRESET causes the 750GX to take a system reset exception. This exception modifies the MSR,
SRR0, and SRR1, as described in the PowerPC Microprocessor Family: The Programming Environments
Manual. Unlike a hard reset, a soft reset does not directly affect the states of output signals. Attempts to use
SRESET during a hard reset sequence or while the Joint Test Action Group (JTAG) logic is non-idle cause
unpredictable results (see Section 7.2.10.2, Soft Reset (SRESET)—Input, on page 272 for more information).
SRESET can be asserted during HRESET assertion (see Figure 4-1). In all three cases shown in Table 4-1,
the SRESET assertion and deassertion have no effect on the operation or state of the machine. SRESET
asserted coincident to, or after the assertion of, HRESET will also have no effect on the operation or state of
the machine.
the SRESET assertion and deassertion have no effect on the operation or state of the machine. SRESET
asserted coincident to, or after the assertion of, HRESET will also have no effect on the operation or state of
the machine.
4.5.1.2 Hard Reset
A hard reset is initiated by asserting HRESET. A hard reset is used primarily for power-on reset (POR) (in
which case test reset (TRST) must also be asserted), but it can also be used to restart a running processor.
The HRESET signal must be asserted during power up and must remain asserted for a period that allows the
phase-locked loop (PLL) to achieve lock and the internal logic to be reset. This period is specified in the
PowerPC 750GX RISC Microprocessor Datasheet. The 750GX tristates all I/O drivers within five clocks of
HRESET assertion. If HRESET is asserted for less than this amount of time, the results are not predictable.
which case test reset (TRST) must also be asserted), but it can also be used to restart a running processor.
The HRESET signal must be asserted during power up and must remain asserted for a period that allows the
phase-locked loop (PLL) to achieve lock and the internal logic to be reset. This period is specified in the
PowerPC 750GX RISC Microprocessor Datasheet. The 750GX tristates all I/O drivers within five clocks of
HRESET assertion. If HRESET is asserted for less than this amount of time, the results are not predictable.
The 750GX’s internal state after the hard reset interval is defined in Table 4-7. If HRESET is asserted during
normal operation, all operations cease, and the machine state is lost (see Section 7.2.10.1, Hard Reset
(HRESET)—Input, on page 272 for more information on a hard reset).
normal operation, all operations cease, and the machine state is lost (see Section 7.2.10.1, Hard Reset
(HRESET)—Input, on page 272 for more information on a hard reset).
Figure 4-1. SRESET Asserted During HRESET
HRESET
SRESET
HRESET
SRESET
HRESET
SRESET
OK
OK
OK