Freescale Semiconductor MPC830x PowerQUICC II Pro Processor Evaluation Kit MPC8309-KIT MPC8309-KIT Fiche De Données
Codes de produits
MPC8309-KIT
MPC8309 PowerQUICC II Pro Integrated Communications Processor Family Hardware Specifications, Rev. 2
Freescale Semiconductor
13
RESET initialization
4.2
AC electrical characteristics
The primary clock source for the MPC8309 can be one of two inputs, SYS_CLK_IN or PCI_SYNC_IN,
depending on whether the device is configured in PCI host or agent mode. The following table provides
the clock input (SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These
specifications are also applicable for QE_CLK_IN.
depending on whether the device is configured in PCI host or agent mode. The following table provides
the clock input (SYS_CLK_IN/PCI_SYNC_IN) AC timing specifications for the MPC8309. These
specifications are also applicable for QE_CLK_IN.
5
RESET initialization
This section describes the AC electrical specifications for the reset initialization timing requirements of
the MPC8309. The following table provides the reset initialization AC timing specifications for the reset
component(s).
the MPC8309. The following table provides the reset initialization AC timing specifications for the reset
component(s).
Table 8. SYS_CLK_IN AC timing specifications
Parameter/Condition
Symbol
Min
Typical
Max
Unit
Note
SYS_CLK_IN frequency
f
SYS_CLK_IN
24 —
66.67
MHz
1
SYS_CLK_IN cycle time
t
SYS_CLK_IN
15
—
41.6
ns
—
SYS_CLK_IN rise and fall time
t
KH
, t
KL
1.1
—
2.8
ns
2
PCI_SYNC_IN rise and fall time
t
PCH
, t
PCL
1.1
—
2.8
ns
2
SYS_CLK_IN duty cycle
t
KHK
/t
SYS_CLK_
IN
40
—
60
%
3
SYS_CLK_IN jitter
—
—
—
±150
ps
4, 5
Notes:
1.
Caution:
The system, core and QUICC Engine block must not exceed their respective maximum or minimum operating
frequencies.
2. Rise and fall times for SYS_CLK_IN are measured at 0.33 and 2.97 V.
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
3. Timing is guaranteed by design and characterization.
4. This represents the total input jitter—short term and long term—and is guaranteed by design.
5. The SYS_CLK_IN driver’s closed loop jitter bandwidth should be < 500 kHz at –20 dB. The bandwidth must be set low to
allow cascade-connected PLL-based devices to track SYS_CLK_IN drivers with the specified jitter.
6. Spread spectrum is allowed up to 1% down-spread @ 33kHz (max rate).
Table 9. RESET initialization timing specifications
Parameter/Condition
Min
Max
Unit
Note
Required assertion time of HRESET to activate reset flow
32
—
t
SYS_CLK_IN
1
Required assertion time of PORESET with stable clock applied to
SYS_CLK_IN or PCI_SYNC_IN (in agent mode)
SYS_CLK_IN or PCI_SYNC_IN (in agent mode)
32
—
t
SYS_CLK_IN
1
HRESET assertion (output)
512
—
t
SYS_CLK_IN
1