Freescale Semiconductor MPC830x PowerQUICC II Pro Processor Evaluation Kit MPC8309-KIT MPC8309-KIT Fiche De Données

14

Freescale Semiconductor

 

The following table provides the PLL lock times.

The following table provides the DC electrical characteristics for the MPC8309 reset signals mentioned in 

.

This section describes the DC and AC electrical specifications for the DDR2 SDRAM interface of the 
MPC8309. Note that DDR2 SDRAM is GV

DD

(typ) = 1.8 V.

The following table provides the recommended operating conditions for the DDR2 SDRAM component(s) 
of the MPC8309 when GV

DD

(typ) = 1.8 V

.

The following table provides the DDR2 capacitance when GV

DD

(typ) = 1.8 V.

Input setup time for POR configuration signals 
(CFG_RESET_SOURCE[0:3]) with respect to negation of PORESET

4

—

t

SYS_CLK_IN

1, 2

Input hold time for POR config signals with respect to negation of 
HRESET 

0

—

ns

1, 

2

1.  t

SYS_CLK_IN

 is the clock period of the input clock applied to SYS_CLK_IN. For more details, see the MPC8309

 PowerQUICC 

II Pro Integrated Communications Processor Family Reference Manual.

2.  POR configuration signals consist of CFG_RESET_SOURCE[0:3].

PLL lock times

—

100

μs

—

Output high voltage

V

OH

I

OH

= –6.0 mA 

2.4

—

V

1

Output low voltage

V

OL

 I

OL

= 6.0 mA

—

0.5

V

1

Output low voltage

V

OL

I

OL

= 3.2 mA

—

0.4

V

1

Input high voltage

V

IH

—

2.0

OV

DD

+ 0.3

V

1

Input low voltage

V

IL

—

–0.3

0.8

V

—

Input current 

I

IN

0 V

≤ V

IN

 

≤ OV

DD

— ±

5

μA

—

 

1. This specification applies when operating from 3.3 V supply.