Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ Fiche De Données

 

Rev. 0 | Page 27 of 40 

The 

 differential outputs conform to the ANSI-644 LVDS 

standard on default power-up. This can be changed to a low power, 
reduced signal option (similar to the IEEE 1596.3 standard) via the 
SPI. The LVDS driver current is derived on chip and sets the 
output current at each output equal to a nominal 3.5 mA. A 100 Ω 
differential termination resistor placed at the LVDS receiver 
inputs results in a nominal 350 mV swing (or 700 mV p-p 
differential) at the receiver.  

When operating in reduced range mode, the output current is 
reduced to 2 mA. This results in a 200 mV swing (or 400 mV p-p 
differential) across a 100 Ω termination at the receiver. 

 LVDS outputs facilitate interfacing with LVDS 

receivers in custom ASICs and FPGAs for superior switching 
performance in noisy environments. Single point-to-point net 
topologies are recommended with a 100 Ω termination resistor  
placed as close to the receiver as possible. If there is no far-end 
receiver termination or there is poor differential trace routing, 
timing errors may result. To avoid such timing errors, it is 
recommended that the trace length be less than 24 inches and 
that the differential output traces be close together and at equal 
lengths. An example of the FCO and data stream with proper 
trace length and position is shown in Figure 70. Figure 71 shows 
the LVDS output timing example in reduced range mode. 

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An example of the LVDS output using the ANSI-644 standard 
(default) data eye and a time interval error (TIE) jitter histo-
gram with trace lengths less than 24 inches on standard FR-4 
material is shown in Figure 72.  

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