Analog Devices AD9253 Evaluation Board AD9253-125EBZ AD9253-125EBZ Fiche De Données
Codes de produits
AD9253-125EBZ
AD9253
Data Sheet
Rev. 0 | Page 26 of 40
Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(f
clock input. The degradation in SNR at a given input frequency
(f
A
) due only to aperture jitter (t
J
) can be calculated by
SNR Degradation = 20 log
10
J
A
t
f
2
1
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 68).
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 68).
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
where aperture jitter may affect the dynamic range of the
.
Power supplies for clock drivers should be separated from the
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
ADC output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter, crystal-controlled oscillators make
the best clock sources. If the clock is generated from another
type of source (by gating, dividing, or other methods), it should
be retimed by the original clock at the last step.
Refer to the
and the
for more in-depth information about jitter
performance as it relates to ADCs.
1
10
100
1000
16 BITS
14 BITS
12 BITS
30
40
50
60
70
80
90
100
110
120
130
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
1.0ps
2.0ps
ANALOG INPUT FREQUENCY (MHz)
10 BITS
8 BITS
RMS CLOCK JITTER REQUIREMENT
S
N
R (
d
B)
10065
-070
Figure 68. Ideal SNR vs. Input Frequency and Jitter
POWER DISSIPATION AND POWER-DOWN MODE
As shown in Figure 69, the power dissipated by the
proportional to its sample rate. The digital power dissipation
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
does not vary significantly because it is determined primarily by
the DRVDD supply and bias current of the LVDS output drivers.
350
300
250
200
150
100
10
130
A
NA
L
O
G
CO
RE
P
O
W
E
R (
m
W
)
SAMPLE RATE (MSPS)
10
065-
07
1
20
30
40
50
60
70
80
90
100 110
120
50 MSPS
80 MSPS
125 MSPS
40 MSPS
20 MSPS
65 MSPS
105 MSPS
Figure 69. Analog Core Power vs. f
SAMPLE
for f
IN
= 10.3 MHz
port or by asserting the PDWN pin high. In this state, the ADC
typically dissipates 2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the
typically dissipates 2 mW. During power-down, the output
drivers are placed in a high impedance state. Asserting the
PDWN pin low returns the
to its normal operating
mode. Note that PDWN is referenced to the digital output
driver supply (DRVDD) and should not exceed that supply
voltage.
driver supply (DRVDD) and should not exceed that supply
voltage.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When
using the SPI port interface, the user can place the ADC in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details on using these features.
shutting down the reference, reference buffer, biasing networks,
and clock. Internal capacitors are discharged when entering
power-down mode and then must be recharged when returning
to normal operation. As a result, wake-up time is related to the
time spent in power-down mode, and shorter power-down
cycles result in proportionally shorter wake-up times. When
using the SPI port interface, the user can place the ADC in
power-down mode or standby mode. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required. See the Memory Map section
for more details on using these features.