Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
377
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
19.4.6.2 Brownout Detector Reset
The brownout detector provides the bodcore_in signal to the SUPC which indicates that the voltage regulation is
operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is
enabled, the Supply Controller asserts vddcore_nreset if BODRSTEN is written to 1 in SUPC_MR.
operating as programmed. If this signal is lost for longer than 1 slow clock period while the voltage regulator is
enabled, the Supply Controller asserts vddcore_nreset if BODRSTEN is written to 1 in SUPC_MR.
If BODRSTEN is set and the voltage regulation is lost (output voltage of the regulator too low), the vddcore_nreset
signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The
BODRSTS bit is set in SUPC_SR so that the user can know the source of the last reset.
signal is asserted for a minimum of 1 slow clock cycle and then released if bodcore_in has been reactivated. The
BODRSTS bit is set in SUPC_SR so that the user can know the source of the last reset.
Until bodcore_in is deactivated, the vddcore_nreset signal remains active.
19.4.7 Wake-up Sources
The wake-up events allow the device to exit backup mode. When a wake-up event is detected, the Supply
Controller performs a sequence which automatically reenables the core power supply.
Controller performs a sequence which automatically reenables the core power supply.
Figure 19-4.
Wake-up Sources
19.4.7.1 Force Wake-up
The FWUP pin is enabled as a wake-up source by writing the FWUPEN bit to 1 in SUPC_WUMR. The FWUPDBC
field in the same register then selects the debouncing period, which can be selected between 3, 32, 512, 4,096 or
32,768 slow clock cycles, corresponding to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1
second, respectively (for a typical slow clock frequency of 32 kHz). Programming FWUPDBC to 0x0 selects an
immediate wake-up, i.e., the FWUP must be low during at least one slow clock period to wake up the core power
supply.
field in the same register then selects the debouncing period, which can be selected between 3, 32, 512, 4,096 or
32,768 slow clock cycles, corresponding to about 100 µs, about 1 ms, about 16 ms, about 128 ms and about 1
second, respectively (for a typical slow clock frequency of 32 kHz). Programming FWUPDBC to 0x0 selects an
immediate wake-up, i.e., the FWUP must be low during at least one slow clock period to wake up the core power
supply.
WKUP15
WKUPEN15
WKUPT15
WKUPEN1
WKUPEN0
Debouncer
SLCK
WKUPDBC
WKUPS
RTCEN
rtc_alarm
SMEN
sm_out
Core
Supply
Restart
Supply
Restart
WKUPIS0
WKUPIS1
WKUPIS15
WKUPT0
WKUPT1
WKUP0
WKUP1
RTTEN
rtt_alarm
Debouncer
RTCOUT0
LPDBC
Debouncer
LPDBC
RTCOUT0
LPDBCS0
LPDBCS1
LPDBCEN1
Low/High
Level Detect
WKUPT1
LPDBCEN0
Low/High
Level Detect
WKUPT0
Low/High
Level Detect
Low/High
Level Detect
Low/High
Level Detect
Low-power
Tamper Detection
Logic
Tamper Detection
Logic