Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

After the end of the current access, if no other request is pending, the slave remains connected to the last master
that performed an access request.

This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non
privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful
for masters that mainly perform single accesses or short bursts with some Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput whatever is the number of requesting masters.

After the end of the current access, if no other request is pending, the slave connects to its fixed default master.
Unlike the last access master, the fixed default master does not change unless the user modifies it by software
(FIXED_DEFMSTR field of the related MATRIX_SCFG).

This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave.
All requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-
privileged masters will get one latency cycle. This technique is useful for a master that mainly performs single
accesses or short bursts with Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus
throughput, regardless of the number of requesting masters.

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e. when two or
more masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus
arbitrating each slave specifically.

The Bus Matrix provides the user with the possibility of choosing between 2 arbitration types or mixing them for
each slave:

1.

Round-robin Arbitration (default)

2.

Fixed Priority Arbitration

The resulting algorithm may be complemented by selecting a default master configuration for each slave.

When re-arbitration must be done, specific conditions apply. See 

Each arbiter has the ability to arbitrate between two or more different master requests. In order to avoid burst
breaking and also to provide the maximum throughput for slave interfaces, arbitration may only take place during
the following cycles:

1.

Idle Cycles: When a slave is not connected to any master or is connected to a master which is not currently 
accessing it.

2.

Single Cycles: When a slave is currently doing a single access.

3.

End of Burst Cycles: When the current cycle is the last cycle of a burst transfer. For defined length burst, 
predicted end of burst matches the size of the transfer but is managed differently for undefined length burst. 
See 

4.

Slot Cycle Limit: When the slot cycle counter has reached the limit value indicating that the current master 
access is too long and must be broken. See