Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

After reset, all the masters belong to the lowest priority pool (MxPR = 0) and are therefore granted bus access in a
true round-robin order.

The highest priority pool must be specifically reserved for masters requiring very low access latency. If more than
one master belongs to this pool, they will be granted bus access in a biased round-robin manner which allows tight
and deterministic maximum access latency from AHB bus requests. In the worst case, any currently occurring
high-priority master request will be granted after the current bus master access has ended and other high priority
pool master requests, if any, have been granted once each.

The lowest priority pool shares the remaining bus bandwidth between AHB Masters.

Intermediate priority pools allow fine priority tuning. Typically, a moderately latency-critical master or a bandwidth-
only critical master will use such a priority level. The higher the priority level (MxPR value), the higher the master
priority.

All combinations of MxPR values are allowed for all masters and slaves. For example, some masters might be
assigned the highest priority pool (round-robin), and remaining masters the lowest priority pool (round-robin), with
no master for intermediate fix priority levels.

If more than one master requests the slave bus, regardless of the respective masters priorities, no master will be
granted the slave bus for two consecutive runs. A master can only get back-to-back grants so long as it is the only
requesting master.

Fixed priority arbitration algorithm is the first and only arbitration algorithm applied between masters from distinct
priority pools. It is also used in priority pools other than the highest and lowest priority pools (intermediate priority
pools).

Fixed priority arbitration allows the Bus Matrix arbiters to dispatch the requests from different masters to the same
slave by using the fixed priority defined by the user in the MxPR field for each master in the Priority Registers,
MATRIX_PRAS and MATRIX_PRBS. If two or more master requests are active at the same time, the master with
the highest priority MxPR number is serviced first.

In intermediate priority pools, if two or more master requests with the same priority are active at the same time, the
master with the highest number is serviced first.

This algorithm is only used in the highest and lowest priority pools. It allows the Bus Matrix arbiters to properly
dispatch requests from different masters to the same slave. If two or more master requests are active at the same
time in the priority pool, they are serviced in a round-robin increasing master number order.

The System I/O Configuration register (CCFG_SYSIO) allows to configure some I/O lines in System I/O mode
(such as JTAG, ERASE, USB, etc...) or as general purpose I/O lines. Enabling or disabling the corresponding I/O
lines in peripheral mode or in PIO mode (PIO_PER or PIO_PDR registers) in the PIO controller as no effect.
However, the direction (input or output), pull-up, pull-down and other mode control is still managed by the PIO
controller.

The SMC Nand Flash Chip Select Configuration Register (CCFG_SMCNFCS) allow to manage  the chip select
signal (NCSx) as assigned to NAND Flash or not.

Each NCSx can be individually assigned to Nand Flash or not. When the NCSx is assigned to NANDFLASH, the
signals NANDOE and NANDWE are used for the NCSx signals selected.