Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

798

 shows the behavior of Transmission Register Empty (TXEMPTY), End of RX buffer (ENDRX), End of

TX buffer (ENDTX), RX Buffer Full (RXBUFF) and TX Buffer Empty (TXBUFE) status flags within the SPI_SR
during an 8-bit data transfer in Fixed mode with the Peripheral Data Controller involved. The PDC is programmed
to transfer and receive three data. The next pointer and counter are not used. The RDRF and TDRE are not shown
because these flags are managed by the PDC when using the PDC.

The SPI Baud rate clock is generated by dividing the peripheral clock by a value between 1 and 255. 

If the SCBR field in the SPI_CSR is programmed to 1, the operating baud rate is peripheral clock (see the
electrical characteristics section for the SPCK maximum frequency). Triggering a transfer while SCBR is at 0 can
lead to unpredictable results. 

At reset, SCBR is 0 and the user has to program it to a valid value before performing the first transfer.

The divisor can be defined independently for each chip select, as it has to be programmed in the SCBR field. This
allows the SPI to automatically adapt the baud rate for each interfaced peripheral without reprogramming. 

 shows a chip select transfer change and consecutive transfers on the same chip select. Three delays

can be programmed to modify the transfer waveforms:



Delay between the chip selects—programmable only once for all chip selects by writing the DLYBCS field in 
the SPI_MR. The SPI slave device deactivation delay is managed through DLYBCS. If there is only one SPI 
slave device connected to the master, the DLYBCS field does not need to be configured. If several slave 
devices are connected to a master, DLYBCS must be configured depending on the highest deactivation 
delay. Refer to the SPI slave device electrical characteristics.



Delay before SPCK—independently programmable for each chip select by writing the DLYBS field. The SPI 
slave device activation delay is managed through DLYBS. Refer to the SPI slave device electrical 
characteristics to define DLYBS.

6

5

4

3

2

1

SPCK

MOSI

(from master)

NPCS0

MSB

LSB

6

5

4

3

2

1

1

2

3

ENDTX

TXEMPTY

MSB

LSB

6

5

4

3

2

1

6

5

4

3

2

1

MISO

(from slave)

6

5

4

3

2

1

6

5

4

3

2

1

ENDRX

TXBUFE

RXBUFF

TDRE

(not required

if PDC is used)

PDC loads first byte

PDC loads 2nd byte

(double buffer effect)

PDC loads last byte

MSB

MSB

MSB

MSB

LSB

LSB

LSB

LSB