Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
800
The variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the
SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
destination peripheral. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to16) to be
transferred through MISO and MOSI lines with the chip select configuration registers (SPI_CSRx). This is not the
optimal means in terms of memory size for the buffers, but it provides a very effective means to exchange data
with several peripherals without any intervention of the processor.
SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
destination peripheral. Using the PDC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to16) to be
transferred through MISO and MOSI lines with the chip select configuration registers (SPI_CSRx). This is not the
optimal means in terms of memory size for the buffers, but it provides a very effective means to exchange data
with several peripherals without any intervention of the processor.
Transfer Size
Depending on the data size to transmit, from 8 to 16 bits, the PDC manages automatically the type of pointer size
it has to point to. The PDC performs the following transfer, depending on the mode and number of bits per data.
it has to point to. The PDC performs the following transfer, depending on the mode and number of bits per data.
Fixed mode:
̶
8-bit data:
1-Byte transfer,
PDC pointer address = address + 1 byte,
PDC counter = counter - 1
1-Byte transfer,
PDC pointer address = address + 1 byte,
PDC counter = counter - 1
̶
8-bit to 16-bit data:
2-Byte transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC pointer address = address + 2 bytes,
PDC counter = counter - 1
2-Byte transfer. n-bit data transfer with don’t care data (MSB) filled with 0’s,
PDC pointer address = address + 2 bytes,
PDC counter = counter - 1
Variable mode:
̶
In Variable mode, PDC pointer address = address +4 bytes and PDC counter = counter - 1 for 8 to 16-
bit transfer size.
bit transfer size.
̶
When using the PDC, the TDRE and RDRF flags are handled by the PDC. The user’s application
does not have to check these bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer
Full (RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral
DMA Controller and user interface, refer to the PDC section of the product datasheet.
does not have to check these bits. Only End of RX Buffer (ENDRX), End of TX Buffer (ENDTX), Buffer
Full (RXBUFF), TX Buffer Empty (TXBUFE) are significant. For further details about the Peripheral
DMA Controller and user interface, refer to the PDC section of the product datasheet.
35.7.3.7 SPI Direct Access Memory Controller (DMAC)
In both Fixed and Variable modes, the Direct Memory Access Controller (DMAC) can be used to reduce processor
overhead.
overhead.
The fixed peripheral selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the
peripheral selection is modified, the SPI_MR must be reprogrammed.
means, as the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, if the
peripheral selection is modified, the SPI_MR must be reprogrammed.
The variable peripheral selection allows buffer transfers with multiple peripherals without reprogramming the
SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
destination peripheral. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to 16) to be
transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal
means in terms of memory size for the buffers, but it provides a very effective means to exchange data with
several peripherals without any intervention of the processor.
SPI_MR. Data written in the SPI_TDR is 32 bits wide and defines the real data to be transmitted and the
destination peripheral. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the
PCS and LASTXFER fields in the MSBs. However, the SPI still controls the number of bits (8 to 16) to be
transferred through MISO and MOSI lines with the chip select configuration registers. This is not the optimal
means in terms of memory size for the buffers, but it provides a very effective means to exchange data with
several peripherals without any intervention of the processor.
35.7.3.8 Peripheral Chip Select Decoding
The user can program the SPI to operate with up to 15 slave peripherals by decoding the four chip select lines,
NPCS0 to NPCS3 with an external decoder/demultiplexer (refer to
NPCS0 to NPCS3 with an external decoder/demultiplexer (refer to
). This can be enabled by writing a
1 to the PCSDEC bit in the SPI_MR.
When operating without decoding, the SPI makes sure that in any case only one chip select line is activated, i.e.,
one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select
is driven low.
one NPCS line driven low at a time. If two bits are defined low in a PCS field, only the lowest numbered chip select
is driven low.