Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données
Codes de produits
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
844
The write mode is defined as a data transmission from the master.
After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded,
SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case).
Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR.
If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset.
describes the Write operation.
Figure 36-27. Write Access Ordered by a Master
Notes:
1. When SVACC is low, the state of SVREAD becomes irrelevant.
2. RXRDY is set when data has been transmitted from the internal shifter to the TWI_RHR and reset when this data is read.
General Call
The general call is performed in order to change the address of the slave.
If a GENERAL CALL is detected, GACC is set.
After the detection of General Call, it is up to the programmer to decode the commands which come afterwards.
In case of a WRITE command, the programmer has to decode the programming sequence and program a new
SADR if the programming sequence matches.
SADR if the programming sequence matches.
describes the General Call access.
Figure 36-28. Master Performs a General Call
Note:
This method allows the user to create an own programming sequence by choosing the programming bytes and the
number of them. The programming sequence has to be provided to the master.
number of them. The programming sequence has to be provided to the master.
Clock Synchronization
In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the
emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching
mechanism is implemented.
emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching
mechanism is implemented.
RXRDY
Read RHR
SVREAD has to be taken into account only while SVACC is active
TWD
SVACC
SVREAD
EOSVACC
SADR does not match,
TWI answers with a NACK
SADR
S
ADR
W
NA
W
A
DATA
A
A
DATA
NA
S/Sr
DATA
NA
P/S/Sr
SADR matches,
TWI answers with an ACK
0000000 + W
GENERAL CALL
P
S
A
GENERAL CALL
Reset or write DADD
A
New SADR
DATA1
A
DATA2
A
A
New SADR
Programming sequence
TXD
GCACC
SVACC
RESET command = 00000110X
WRITE command = 00000100X
Reset after read