Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Fiche De Données

845

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14



Clock Synchronization in Read Mode

The clock is tied low if the internal shifter is empty and if a STOP or REPEATED START condition was not 
detected. It is tied low until the internal shifter is loaded.

 describes the clock synchronization in Read mode.

Notes:

1. TXRDY is reset when data has been written in the TWI_THR to the internal shifter and set when this data has been 

acknowledged or non acknowledged.

2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from 

SADR.

3. SCLWS is automatically set when the clock synchronization mechanism is started.



Clock Synchronization in Write Mode

The clock is tied low if the internal shifter and the TWI_RHR is full. If a STOP or REPEATED_START 
condition was not detected, it is tied low until TWI_RHR is read.

 describes the clock synchronization in Write mode.

DATA1

The clock is stretched after the ACK, the state of TWD is undefined during clock stretching

SCLWS

SVACC

SVREAD

TXRDY

TWCK

TWI_THR

TXCOMP

The data is memorized in TWI_THR until a new value is written

TWI_THR is transmitted to the shift register

Ack or Nack from the master

DATA0

DATA0

DATA2

1

2

1

CLOCK is tied low by the TWI

as long as THR is empty

S

SADR

S

R

DATA0

A

A

DATA1

A

DATA2

NA

S

XXXXXXX

2

Write THR

As soon as a START is detected