Manuel D’Utilisation (HD8450WCGHBOX)Table des matièresRevision History3Processor Identification5Table 1. CPUID Values for AMD Family 10h Processor Revisions5Table 2. Supported Mixed Silicon Revision Configurations6Table 3. String Table Reference Per Package Type8Table 4. String1 Values for Socket Fr2 (1207) Processors9Table 5. String2 Values for Socket Fr2 (1207) Processors9Table 6. String1 Values for Socket AM2r2 Processors10Table 7. String2 Values for Socket AM2r2 Processors10F4x164 Fixed Errata Register11MSRC001_0140 OS Visible Work-around MSR0 (OSVW_ID_Length)12Table 8. OSVW_ID_Length Per Processor Revision12MSRC001_0141 OS Visible Work-around MSR1 (OSVW_Status)13Product Errata14Table 9. Cross-Reference of Product Revision to Errata14Table 10. Cross-Reference of Errata to Processor Segments16Table 11. Cross-Reference of Errata to Package Type1757 Some Data Cache Tag Eviction Errors Are Reported As Snoop Errors1860 Single Machine Check Error May Report Overflow1977 Long Mode CALLF or JMPF May Fail To Signal GP When Callgate Descriptor is Beyond GDT/LDT Limit20178 Default RdPtrInit Value Does Not Provide Sufficient Timing Margin21244 A DIV Instruction Followed Closely By Other Divide Instructions May Yield Incorrect Results22246 Breakpoint Due to An Instruction That Has an Interrupt Shadow May Be Delivered to the Hypervisor23248 INVLPGA of A Guest Page May Not Invalidate Splintered Pages24254 Internal Resource Livelock Involving Cached TLB Reload25260 REP MOVS Instruction May Corrupt Source Address26261 Processor May Stall Entering Stop-Grant Due to Pending Data Cache Scrub27263 Incompatibility With Some DIMMs Due to DQS Duty Cycle Distortion28264 Incorrect DRAM Data Masks Asserted When DRAM Controller Data Interleaving Is Enabled29269 ITT Specification Exceeded During Power-Up Sequencing30273 Lane Select Function Is Not Available for Link BIST on 8-Bit HyperTransport™ Links In Ganged Mode31274 IDDIO Specification Exceeded During Power-Up Sequencing32278 Incorrect Memory Controller Operation In Ganged Mode33279 HyperTransport™ Link RTT and RON Specification Violations34280 Time Stamp Counter May Yield An Incorrect Value35293 Memory Instability After PWROK Assertion36295 DRAM Phy Configuration Access Failures37297 Single Machine Check Error May Report Overflow38298 L2 Eviction May Occur During Processor Operation To Set Accessed or Dirty Bit39300 Hardware Memory Clear Is Not Supported After Software DRAM Initialization40301 Performance Counters Do Not Accurately Count MFENCE or SFENCE Instructions41302 MWAIT Power Savings May Not Be Realized when Two or More Cores Monitor the Same Address42308 Processor Stall in C1 Low Power State43309 Processor Core May Execute Incorrect Instructions on Concurrent L2 and Northbridge Response44312 CVTSD2SS and CVTPD2PS Instructions May Not Round to Zero45315 FST and FSTP Instructions May Calculate Operand Address in Incorrect Mode46319 Inaccurate Temperature Measurement47Documentation Support48Taille: 210 koPages: 48Language: EnglishOuvrir le manuel
