Fiche De DonnéesTable des matièresOperating Conditions1Core: 16-Bit dsPIC33F CPU1Clock Management1Power Management1Advanced Analog Features1Timers/Output Compare/Input Capture1Communication Interfaces1Input/Output1Qualification and Class B Support1Debugger Development Support1dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Product Families2Pin Diagrams3Pin Diagrams (Continued)4Pin Diagrams (Continued)5Table of Contents6Most Current Data Sheet7Errata7Customer Notification System7Referenced Sources81.0 Device Overview9FIGURE 1-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Block Diagram10TABLE 1-1: Pinout I/O Descriptions (Continued)112.0 Guidelines for Getting Started with 16-bit Digital Signal Controllers132.1 Basic Connection Requirements132.2 Decoupling Capacitors13FIGURE 2-1: Recommended Minimum connection142.2.1 Tank Capacitors142.3 CPU Logic Filter Capacitor Connection (Vcap)142.4 Master Clear (MCLR) Pin14FIGURE 2-2: Example of MCLR Pin Connections142.5 ICSP Pins152.6 External Oscillator Pins15FIGURE 2-3: Suggested Placement of the Oscillator Circuit152.7 Oscillator Value Conditions on Device Start-up162.8 Configuration of Analog and Digital Pins During ICSP Operations162.9 Unused I/Os163.0 CPU173.1 Data Addressing Overview173.2 DSP Engine Overview173.3 Special MCU Features18FIGURE 3-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 CPU Core Block Diagram18FIGURE 3-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Programmer’s Model193.4 CPU Resources203.4.1 Key Resources203.5 CPU Control Registers21Register 3-1: SR: CPU Status Register (Continued)21Register 3-2: CORCON: CORE Control Register233.6 Arithmetic Logic Unit (ALU)243.6.1 Multiplier243.6.2 Divider243.7 DSP Engine24TABLE 3-1: DSP Instructions Summary24FIGURE 3-3: DSP Engine Block Diagram253.7.1 Multiplier263.7.2 Data Accumulators and Adder/Subtracter263.7.3 Barrel Shifter284.0 Memory Organization294.1 Program Address Space29FIGURE 4-1: Program Memory for dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Devices294.1.1 Program Memory Organization304.1.2 Interrupt and Trap Vectors30FIGURE 4-2: Program Memory Organization304.2 Data Address Space314.2.1 Data Space Width314.2.2 Data Memory Organization and Alignment314.2.3 SFR Space314.2.4 Near Data Space31FIGURE 4-3: Data Memory Map for dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Devices with 2 Kbytes RAM324.2.5 X and Y Data Spaces334.3 Program Memory Resources334.3.1 Key Resources334.4 Special Function Register Maps34TABLE 4-1: CPU Core Registers Map (Continued)34TABLE 4-2: Change Notification Register Map for dsPIC33FJ32GP20235TABLE 4-3: Change Notification Register Map for dsPIC33FJ32GP204 and dsPIC33FJ16GP30435TABLE 4-4: Interrupt Controller Register Map36TABLE 4-5: Timer Register Map37TABLE 4-6: Input Capture Register Map37TABLE 4-7: Output Compare Register Map37TABLE 4-8: I2C1 Register Map38TABLE 4-9: UART1 Register Map38TABLE 4-10: SPI1 Register Map38TABLE 4-11: peripheral pin select input register map39TABLE 4-12: peripheral pin select output register map for dsPIC33FJ32GP20239TABLE 4-13: pERIPHERAL pin select outPUT Register Map for dsPIC33FJ32GP204 and dsPIC33FJ16GP30440TABLE 4-14: ADC1 Register Map for dsPIC33FJ32GP204 and dsPIC33FJ16GP30441TABLE 4-15: ADC1 Register Map for dsPIC33FJ32GP20242TABLE 4-16: PORTA Register Map for dsPIC33FJ32GP20243TABLE 4-17: PORTA Register Map for dsPIC33FJ32GP204 and dsPIC33FJ16GP30443TABLE 4-18: PORTB Register Map43TABLE 4-19: PORTC Register Map for dsPIC33FJ32GP204 and dsPIC33FJ16GP30443TABLE 4-20: System Control Register Map44TABLE 4-21: NVM Register Map44TABLE 4-22: PMD Register Map444.4.1 Software Stack45FIGURE 4-4: CALL Stack Frame454.4.2 Data Ram Protection Feature454.5 Instruction Addressing Modes454.5.1 File Register Instructions454.5.2 MCU Instructions45TABLE 4-23: Fundamental Addressing Modes Supported464.5.3 Move and Accumulator Instructions464.5.4 MAC Instructions464.5.5 Other Instructions464.6 Modulo Addressing474.6.1 Start and End Address474.6.2 W Address Register Selection47FIGURE 4-5: Modulo Addressing Operation Example474.6.3 Modulo Addressing Applicability484.7 Bit-Reversed Addressing484.7.1 Bit-Reversed Addressing Implementation48FIGURE 4-6: Bit-Reversed Address Example49TABLE 4-24: Bit-Reversed Address Sequence (16-Entry)494.8 Interfacing Program and Data Memory Spaces504.8.1 Addressing Program Space50TABLE 4-25: Program Space Address Construction50FIGURE 4-7: Data Access from Program Space Address Generation514.8.2 Data Access From Program Memory Using Table Instructions52FIGURE 4-8: Accessing Program Memory with Table Instructions524.8.3 Reading Data from Program Memory Using Program Space Visibility53FIGURE 4-9: Program Space Visibility Operation535.0 Flash Program Memory555.1 Table Instructions and Flash Programming55FIGURE 5-1: Addressing for Table Registers555.2 RTSP Operation565.3 Programming Operations56EQUATION 5-1: programming time56EQUATION 5-2: Minimum Row Write Time56EQUATION 5-3: Maximum Row Write Time565.4 Flash Memory Resources565.4.1 Key Resources565.5 Control Registers56Register 5-1: NVMCON: Flash Memory Control Register57Register 5-2: NVMKEY: Nonvolatile Memory Key Register585.5.1 Programming Algorithm for Flash Program Memory59EXAMPLE 5-1: Erasing a Program Memory Page59EXAMPLE 5-2: Loading the Write Buffers60EXAMPLE 5-3: Initiating a Programming Sequence606.0 Resets61FIGURE 6-1: Reset module Block Diagram616.1 Resets Resources626.1.1 Key Resources626.2 Reset Control Registers63Register 6-1: RCON: Reset Control Register(1) (Continued)636.3 System Reset65TABLE 6-1: Oscillator Delay65FIGURE 6-2: System Reset Timing66TABLE 6-2: Oscillator Parameters676.4 Power-on Reset (POR)676.4.1 Brown-out Reset (BOR) and Power-up timer (PWRT)67FIGURE 6-3: Brown-out Situations686.5 External Reset (EXTR)686.5.1 External supervisory circuit686.5.2 Internal Supervisory Circuit686.6 Software RESET Instruction (SWR)686.7 Watchdog Time-out Reset (WDTO)686.8 Trap Conflict Reset686.9 Configuration Mismatch Reset696.10 Illegal Condition Device Reset696.10.1 Illegal Opcode Reset696.10.2 Uninitialized W Register Reset696.10.3 Security Reset696.11 Using the RCON Status Bits69TABLE 6-3: Reset Flag Bit Operation697.0 Interrupt Controller717.1 Interrupt Vector Table717.1.1 Alternate interrupt Vector Table717.2 Reset Sequence71FIGURE 7-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Interrupt Vector Table72TABLE 7-1: Interrupt Vectors73TABLE 7-2: Trap Vectors737.3 Interrupt Resources747.3.1 Key Resources747.4 Interrupt Control and Status Registers747.4.1 INTcon1 and intcon2747.4.2 Ifsx747.4.3 Iecx747.4.4 ipcx747.4.5 inttreg747.4.6 status registers74Register 7-1: SR: CPU STATUS Register(1)75Register 7-2: CORCON: CORE Control Register(1)75Register 7-3: INTCON1: Interrupt Control Register 1 (Continued)76Register 7-4: INTCON2: Interrupt Control Register 278Register 7-5: IFS0: Interrupt Flag Status Register 0 (Continued)79Register 7-6: IFS1: Interrupt Flag Status Register 181Register 7-7: IFS4: Interrupt Flag Status Register 482Register 7-8: IEC0: Interrupt Enable Control Register 0 (Continued)83Register 7-9: IEC1: Interrupt Enable Control Register 185Register 7-10: IEC4: Interrupt Enable Control Register 486Register 7-11: IPC0: Interrupt Priority Control Register 087Register 7-12: IPC1: Interrupt Priority Control Register 188Register 7-13: IPC2: Interrupt Priority Control Register 289Register 7-14: IPC3: Interrupt Priority Control Register 390Register 7-15: IPC4: Interrupt Priority Control Register 491Register 7-16: IPC5: Interrupt Priority Control Register 592Register 7-17: IPC7: Interrupt Priority Control Register 793Register 7-18: IPC16: Interrupt Priority Control Register 1694Register 7-19: INTTREG: Interrupt Control and Status Register957.5 Interrupt Setup Procedures967.5.1 Initialization967.5.2 Interrupt Service Routine967.5.3 Trap Service Routine967.5.4 Interrupt Disable968.0 Oscillator Configuration97FIGURE 8-1: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 Oscillator System Diagram978.1 CPU Clocking System988.1.1 System Clock sources988.1.2 System Clock Selection98EQUATION 8-1: Device Operating Frequency988.1.3 PLL Configuration98EQUATION 8-2: Fosc Calculation99EQUATION 8-3: XT with PLL Mode Example99FIGURE 8-2: dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304 PLL Block Diagram99TABLE 8-1: Configuration Bit Values for Clock Selection998.2 Oscillator Resources1008.2.1 Key Resources1008.3 Oscillator Control Registers101Register 8-1: OSCCON: Oscillator Control Register(1,3) (Continued)101Register 8-2: CLKDIV: Clock Divisor Register(2) (Continued)103Register 8-3: PLLFBD: PLL Feedback Divisor Register(1)105Register 8-4: OSCTUN: FRC Oscillator Tuning Register(2)1068.4 Clock Switching Operation1078.4.1 Enabling Clock Switching1078.4.2 Oscillator Switching Sequence1078.5 Fail-Safe Clock Monitor (FSCM)1079.0 Power-Saving Features1099.1 Clock Frequency and Clock Switching1099.2 Instruction-Based Power-Saving Modes1099.2.1 Sleep Mode109EXAMPLE 9-1: PWRSAV Instruction Syntax1099.2.2 Idle Mode1109.2.3 Interrupts Coincident with Power Save Instructions1109.3 Doze Mode1109.4 Peripheral Module Disable1109.5 Power-Saving Resources1119.5.1 Key Resources1119.6 Power-Saving Control Registers112Register 9-1: PMD1: Peripheral Module Disable Control Register 1112Register 9-2: PMD2: Peripheral Module Disable Control Register 211310.0 I/O Ports11510.1 Parallel I/O (PIO) Ports115FIGURE 10-1: Block Diagram of a Typical Shared Port Structure11510.2 Open-Drain Configuration11610.3 Configuring Analog Port Pins11610.4 I/O Port Write/Read Timing11610.5 Input Change Notification116EXAMPLE 10-1: Port Write/Read116EXAMPLE 10-2: PORT Bit Operations11610.6 Peripheral Pin Select11710.6.1 Available Pins11710.6.2 Controlling Peripheral Pin Select117FIGURE 10-2: remappable MUX input for u1rx117TABLE 10-1: rEMAPPABLE PERIPHERAL INPUTS(1)118FIGURE 10-3: multiplexing of remappable output for rpn118TABLE 10-2: OUTPUT selection for remappable pin (RPn)11910.6.3 Controlling Configuration Changes11910.7 I/O Helpful Tips12010.8 I/O Resources12010.8.1 Key Resources12010.9 Peripheral Pin Select Registers121Register 10-1: RPINR0: Peripheral Pin Select Input Register 0121Register 10-2: RPINR1: Peripheral Pin Select Input Register 1122Register 10-3: RPINR3: Peripheral Pin Select Input Register 3123Register 10-4: RPINR7: Peripheral Pin Select Input Register 7124Register 10-5: RPInR10: Peripheral Pin Select Input Register 10125Register 10-6: RPINR11: Peripheral Pin Select Input Register 11126Register 10-7: RPINR18: Peripheral Pin Select Input Register 18127Register 10-8: RPINR20: Peripheral Pin Select Input Register 20128Register 10-9: RPINR21: Peripheral Pin Select Input Register 21129Register 10-10: RPOR0: Peripheral Pin Select Output Register 0130Register 10-11: RPOR1: Peripheral Pin Select Output Register 1130Register 10-12: RPOR2: Peripheral Pin Select Output Register 2131Register 10-13: RPOR3: Peripheral Pin Select Output Register 3131Register 10-14: RPOR4: Peripheral Pin Select Output Register 4132Register 10-15: RPOR5: Peripheral Pin Select Output Register 5132Register 10-16: RPOR6: Peripheral Pin Select Output Register 6133Register 10-17: RPOR7: Peripheral Pin Select Output Register 7133Register 10-18: RPOR8: Peripheral Pin Select Output Register 8134Register 10-19: RPOR9: Peripheral Pin Select Output Register 9134Register 10-20: RPOR10: Peripheral Pin Select Output Register 10135Register 10-21: RPOR11: Peripheral Pin Select Output Register 11135Register 10-22: RPOR12: Peripheral Pin Select Output Register 1213611.0 Timer1137FIGURE 11-1: 16-bit Timer1 Module Block Diagram13711.1 Timer Resources13811.1.1 Key Resources13811.2 Timer1 Control Register139Register 11-1: T1CON: Timer1 Control Register13912.0 Timer2/3 Feature14112.1 32-Bit Operation141FIGURE 12-1: Timer2/3 (32-bit) Block Diagram(1)142FIGURE 12-2: Timer2 (16-bit) Block Diagram14212.2 Timer Resources14312.2.1 Key Resources14312.3 Timer2/3 Control Registers144Register 12-1: T2CON Control Register144Register 12-2: T3CON Control Register14513.0 Input Capture147FIGURE 13-1: Input Capture Block Diagram14713.1 Input Capture Resources14813.1.1 Key Resources14813.2 Input Capture Registers149Register 13-1: ICxCON: Input Capture x Control Register14914.0 Output Compare151FIGURE 14-1: Output Compare Module Block Diagram15114.1 Output Compare Modes152TABLE 14-1: Output Compare Modes152FIGURE 14-2: Output Compare Operation15214.2 Output Compare Resources15314.2.1 Key Resources15314.3 Output Compare Register154Register 14-1: OCxCON: Output Compare x Control Register15415.0 Serial Peripheral Interface (SPI)155FIGURE 15-1: SPI Module Block Diagram15515.1 SPI Helpful Tips15615.2 SPI Resources15615.2.1 Key Resources15615.3 SPI Control Registers157Register 15-1: SPIxSTAT: SPIx Status and Control Register157Register 15-2: SPIxCON1: SPIx Control Register 1 (Continued)158Register 15-3: SPIxCON2: SPIx Control Register 216016.0 Inter-Integrated Circuit™ (I2C™)16116.1 Operating Modes161FIGURE 16-1: I2C™ Block Diagram (x = 1)16216.2 I2C Resources16316.2.1 Key Resources16316.3 I2C Registers163Register 16-1: I2CxCON: I2Cx Control Register (Continued)164Register 16-2: I2CxSTAT: I2Cx Status Register (Continued)166Register 16-3: I2CxMSK: I2Cx Slave Mode Address Mask Register16817.0 Universal Asynchronous Receiver Transmitter (UART)169FIGURE 17-1: UART Simplified Block Diagram16917.1 UART Helpful Tips17017.2 UART Resources17017.2.1 Key Resources17017.3 UART Control Registers171Register 17-1: UxMODE: UARTx Mode Register (Continued)171Register 17-2: UxSTA: UARTx Status and Control Register (Continued)17318.0 10-bit/12-bit Analog-to-Digital Converter (ADC)17518.1 Key Features17518.2 ADC Initialization175FIGURE 18-1: ADC1 Module Block Diagram for dsPIC33FJ16GP304 and dsPIC33FJ32GP204 Devices176FIGURE 18-2: ADC1 Module Block Diagram FOR dsPIC33FJ32GP202 Devices177FIGURE 18-3: ADC Conversion Clock Period Block Diagram17818.3 ADC Helpful Tips17818.4 ADC Resources17818.4.1 Key Resources17818.5 ADC Control Registers179Register 18-1: AD1CON1: ADC1 control register 1 (Continued)179Register 18-2: AD1CON2: ADC1 control register 2181Register 18-3: AD1CON3: ADC1 Control Register 3182Register 18-4: AD1CHS123: ADC1 INPUT Channel 1, 2, 3 select Register (Continued)183Register 18-5: AD1CHS0: ADC1 INPUT Channel 0 select Register (Continued)185Register 18-6: AD1CSSL: ADC1 INPUT SCAN SELECT register Low(1,2)187Register 18-7: AD1PCFGL: ADC1 Port configuration register Low(1,2,3)18719.0 Special Features18919.1 Configuration Bits189TABLE 19-1: Device Configuration Register Map189TABLE 19-2: Configuration Bits Description (Continued)19019.2 On-Chip Voltage Regulator193FIGURE 19-1: Connections for the On-Chip Voltage Regulator(1,2,3)19319.3 BOR: Brown-out Reset19319.4 Watchdog Timer (WDT)19419.4.1 Prescaler/Postscaler19419.4.2 Sleep and Idle Modes19419.4.3 Enabling WDT194FIGURE 19-2: WDT Block Diagram19419.5 JTAG Interface19519.6 Code Protection and CodeGuard™ Security195TABLE 19-3: CODE FLASH SECURITY Segment SIZES FOR 32 KByte Devices195TABLE 19-4: CODE FLASH SECURITY Segment SIZES FOR 16 KByte Devices19519.7 In-Circuit Serial Programming19619.8 In-Circuit Debugger19620.0 Instruction Set Summary197TABLE 20-1: Symbols used in Opcode Descriptions (Continued)198TABLE 20-2: Instruction Set OVERVIEW (Continued)20021.0 Development Support20521.1 MPLAB Integrated Development Environment Software20521.2 MPLAB C Compilers for Various Device Families20621.3 HI-TECH C for Various Device Families20621.4 MPASM Assembler20621.5 MPLINK Object Linker/ MPLIB Object Librarian20621.6 MPLAB Assembler, Linker and Librarian for Various Device Families20621.7 MPLAB SIM Software Simulator20721.8 MPLAB REAL ICE In-Circuit Emulator System20721.9 MPLAB ICD 3 In-Circuit Debugger System20721.10 PICkit 3 In-Circuit Debugger/ Programmer and PICkit 3 Debug Express20721.11 PICkit 2 Development Programmer/Debugger and PICkit 2 Debug Express20821.12 MPLAB PM3 Device Programmer20821.13 Demonstration/Development Boards, Evaluation Kits, and Starter Kits20822.0 Electrical Characteristics209Absolute Maximum Ratings(1)20922.1 DC Characteristics210TABLE 22-1: Operating MIPS vs. Voltage210TABLE 22-2: Thermal Operating Conditions210TABLE 22-3: Thermal Packaging Characteristics210TABLE 22-4: DC Temperature and Voltage specifications211TABLE 22-5: DC Characteristics: Operating Current (Idd)212TABLE 22-6: DC Characteristics: Idle Current (iidle)213TABLE 22-7: DC Characteristics: Power-Down Current (Ipd)214TABLE 22-8: DC Characteristics: doze Current (Idoze)215TABLE 22-9: DC Characteristics: I/O Pin Input Specifications (Continued)216TABLE 22-10: DC Characteristics: I/O Pin Output Specifications218TABLE 22-11: Electrical Characteristics: BOR219TABLE 22-12: DC Characteristics: Program Memory219TABLE 22-13: Internal Voltage Regulator Specifications21922.2 AC Characteristics and Timing Parameters220TABLE 22-14: Temperature and Voltage Specifications – AC220FIGURE 22-1: Load Conditions for Device Timing Specifications220TABLE 22-15: cAPAcITIVE lOADING rEQUIREMENTS ON oUTPUT pINS220FIGURE 22-2: External Clock Timing221TABLE 22-16: External Clock Timing Requirements221TABLE 22-17: PLL Clock Timing Specifications (Vdd = 3.0V to 3.6V)222TABLE 22-18: AC Characteristics: Internal RC Accuracy222TABLE 22-19: Internal RC accuracy222FIGURE 22-3: I/O Timing Characteristics223TABLE 22-20: I/O Timing Requirements223FIGURE 22-4: Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer Timing Characteristics224TABLE 22-21: Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer Timing Requirements225FIGURE 22-5: Timer1, 2 and 3 External Clock Timing Characteristics226TABLE 22-22: Timer1 External Clock Timing Requirements(1)226TABLE 22-23: Timer2 External Clock Timing Requirements227TABLE 22-24: Timer3 External Clock Timing Requirements227FIGURE 22-6: INPUT CAPTURE (CAPx) TIMING Characteristics228TABLE 22-25: Input Capture timing requirements228FIGURE 22-7: Output Compare Module (OCx) Timing Characteristics228TABLE 22-26: Output Compare Module timing requirements228FIGURE 22-8: OC/PWM Module Timing Characteristics229TABLE 22-27: Simple OC/PWM MODE Timing Requirements229TABLE 22-28: SPIx Maximum Data/CLock Rate Summary230FIGURE 22-9: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 0) TIMING CHARACTERISTICS230FIGURE 22-10: SPIx MASTER MODE (Half-Duplex, Transmit Only CKE = 1) TIMING CHARACTERISTICS230TABLE 22-29: SPIx Master Mode (Half-Duplex, Transmit Only) Timing Requirements231FIGURE 22-11: SPIx MASTER MODE (Full-Duplex, CKE = 1, CKP = X, SMP = 1) TIMING CHARACTERISTICS232TABLE 22-30: SPIx Master Mode (Full-Duplex, CKE = 1, CKP = x, SMP = 1) Timing Requirements232FIGURE 22-12: SPIx MASTER MODE (Full-Duplex, CKE = 0, CKP = X, SMP = 1) TIMING CHARACTERISTICS233TABLE 22-31: SPIx Master Mode (Full-Duplex, CKE = 0, CKP = x, SMP = 1) Timing Requirements233FIGURE 22-13: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) TIMING CHARACTERISTICS234TABLE 22-32: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 0, SMP = 0) Timing Requirements235FIGURE 22-14: SPIx SLAVE MODE (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) TIMING CHARACTERISTICS236TABLE 22-33: SPIx Slave Mode (Full-Duplex, CKE = 1, CKP = 1, SMP = 0) Timing Requirements237FIGURE 22-15: SPIx SLAVE MODE (Full-Duplex CKE = 0, CKP = 1, SMP = 0) TIMING CHARACTERISTICS238TABLE 22-34: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 1, SMP = 0) Timing Requirements239FIGURE 22-16: SPIx SLAVE MODE (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) TIMING CHARACTERISTICS240TABLE 22-35: SPIx Slave Mode (Full-Duplex, CKE = 0, CKP = 0, SMP = 0) Timing Requirements241FIGURE 22-17: I2Cx Bus Start/Stop Bits Timing Characteristics (Master Mode)242FIGURE 22-18: I2Cx Bus Data Timing Characteristics (Master mode)242TABLE 22-36: I2Cx Bus Data Timing Requirements (Master Mode)243FIGURE 22-19: I2Cx Bus Start/Stop Bits Timing Characteristics (slave mode)244FIGURE 22-20: I2Cx Bus Data Timing Characteristics (slave mode)244TABLE 22-37: I2Cx Bus Data Timing Requirements (Slave Mode)245TABLE 22-38: ADC Module Specifications246TABLE 22-39: ADC Module Specifications (12-bit Mode)247TABLE 22-40: ADC Module Specifications (10-bit Mode)248FIGURE 22-21: ADC Conversion (12-bit mode) Timing Characteristics (asam = 0, ssrc<2:0> = 000)249TABLE 22-41: ADC Conversion (12-bit Mode) TiminG rEQUIREMENTS249FIGURE 22-22: ADC Conversion (10-bit mode) Timing Characteristics (chps<1:0> = 01, SIMSAM = 0, asam = 0, ssrc<2:0> = 000)250FIGURE 22-23: ADC Conversion (10-bit mode) Timing cHARACTERISTICS (chps<1:0> = 01, SIMSAM = 0, asam = 1, ssrc<2:0> = 111, SAMC<4:0> = 00001)25023.0 High Temperature Electrical Characteristics253Absolute Maximum Ratings(1)25323.1 High Temperature DC Characteristics254TABLE 23-1: Operating MIPS vs. Voltage254TABLE 23-2: Thermal Operating Conditions254TABLE 23-3: DC Temperature and Voltage Specifications254TABLE 23-4: DC Characteristics: Power-down Current (Ipd)255TABLE 23-5: DC Characteristics: Operating Current (Idd)255TABLE 23-6: DC Characteristics: Doze Current (Idoze)255TABLE 23-7: DC Characteristics: I/O Pin Output Specifications25623.2 AC Characteristics and Timing Parameters257TABLE 23-8: Temperature and Voltage Specifications – AC257FIGURE 23-1: Load Conditions for Device Timing Specifications257TABLE 23-9: PLL Clock Timing Specifications257TABLE 23-10: SPIx Master Mode (cke = 0) Timing Requirements258TABLE 23-11: SPIx Module Master Mode (cke = 1) Timing Requirements258TABLE 23-12: SPIx Module Slave Mode (cke = 0) Timing Requirements259TABLE 23-13: SPIx Module Slave Mode (cke = 1) Timing Requirements259TABLE 23-14: Internal RC accuracy259TABLE 23-15: ADC Module Specifications260TABLE 23-16: ADC Module Specifications (12-bit Mode)(3)260TABLE 23-17: ADC Module Specifications (10-bit Mode)(3)261TABLE 23-18: ADC Conversion (12-bit Mode) Timing Requirements262TABLE 23-19: ADC Conversion (10-bit mode) Timing Requirements26224.0 DC and AC Device Characteristics Graphs263FIGURE 24-1: Voh – 2x Driver Pins263FIGURE 24-2: Voh – 4x Driver Pins263FIGURE 24-3: Voh – 8x Driver Pins263FIGURE 24-4: Voh – 16x Driver Pins263FIGURE 24-5: Vol – 2x Driver Pins264FIGURE 24-6: Vol – 4x Driver Pins264FIGURE 24-7: Vol – 8x Driver Pins264FIGURE 24-8: Vol – 16x Driver Pins264FIGURE 24-9: Typical Ipd Current @ Vdd = 3.3V, +85ºC265FIGURE 24-10: Typical Idd Current @ Vdd = 3.3V, +85ºC265FIGURE 24-11: Typical Idoze Current @ Vdd = 3.3V, +85ºC265FIGURE 24-12: Typical Iidle Current @ Vdd = 3.3V, +85ºC265FIGURE 24-13: Typical FRC Frequency @ Vdd = 3.3V266FIGURE 24-14: Typical LPRC Frequency @ Vdd = 3.3V26625.0 Packaging Information26725.1 Package Marking Information26725.1 Package Marking Information (Continued)26825.2 Package Details269Appendix A: Revision History281Revision A (July 2007)281Revision B (June 2008)281TABLE A-1: Major Section Updates (Continued)281Revision C (December 2008)284TABLE A-2: Major Section Updates284Revision D (October 2009)285TABLE A-3: Major Section Updates285Revision E (November 2009)286TABLE A-4: Major Section Updates286Revision F (November 2009)286TABLE A-5: Major Section Updates286Revision G (January 2011)287TABLE A-6: Major Section Updates (Continued)287Revision H (July 2011)289TABLE A-7: Major Section Updates289Revision J (June 2012)289TABLE A-8: Major Section Updates289INDEX291The Microchip Web Site295Customer Change Notification Service295Customer Support295Reader Response296Product Identification System297Taille: 4,4 MoPages: 300Language: EnglishOuvrir le manuel
