NEC PD78F9488 Manuale Utente

User’s Manual  U15331EJ4V1UD

The clock generator generates the following clocks and controls the operation modes of the CPU, such as the 

standby mode. 

 
•  Main system clock     f

X

  

•  Subsystem clock     f

XT

 

•  CPU clock     f

CPU

 

•  Clock to peripheral hardware 
 
The operation and function of the clock generator is determined by the processor clock control register (PCC), 

subclock oscillation mode register (SCKM), and subclock control register (CSS), as follows.  

 

(a)  The low-speed mode (1.6 

µ

s: at 5.0 MHz operation) of the main system clock is selected when the 

RESET signal is generated (PCC = 02H).  While a low level is being to the RESET pin, oscillation of the 
main system clock is stopped. 

 

(b)  Three types of minimum instruction execution time (0.4 

µ

s and 1.6 

µ

s:  main system clock (at 5.0 MHz 

operation), 122 

µ

s:  subsystem clock (at 32.768 kHz operation)) can be selected by the PCC, SCKM, 

and CSS settings.  Also, the subsystem clock can be changed to a clock that uses a circuit to multiply 
the subclock by 4 via a mask option in the 

µ

PD789488 and 789489 or the subclock selection register 

(SSCK) in the 

µ

PD78F9488 and 78F9489 (15.26 

µ

s: a circuit to multiply the subsystem clock by 4 is 

used). 

 

(c)  Two standby modes, STOP and HALT, can be used with the main system clock selected.  In a system 

where the subsystem clock is not used, setting bit 1 (FRC) of SCKM so that the on-chip feedback 
resistor cannot be used reduces current consumption in STOP mode.  In a system where the 
subsystem clock is used, setting SCKM bit 0 to 1 can cause the subsystem clock to stop oscillation. 

 

(d)  CSS bit 4 (CSS0) can be used to select the subsystem clock so that low current consumption operation 

is used (122 

µ

s:  at 32.768 kHz operation). 

 

(e)  With the subsystem clock selected, it is possible to cause the main system clock to stop oscillating 

using bit 7 (MCC) of PCC.  The HALT mode can be used, but the STOP mode cannot. 

 

(f)  The clock pulse for the peripheral hardware is generated by dividing the frequency of the main system 

clock, but the subsystem clock pulse is only supplied to 8-bit timer 50, the watch timer, and the LCD 
controller/driver. 8-bit timer 50, the watch timer, and the LCD controller/driver can therefore keep 
running even during standby.  The other hardware stops when the main system clock stops because it 
runs based on the main system clock (except for external input clock operations).