Texas Instruments TMS320C3x Manuale Utente
1 wait state
required
Pipeline Conflicts
8-12
Example 8–7. Multicycle Program Memory Fetches
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
MPYF
—
—
—
n+1
ADDF
MPYF
—
—
n+2 RDY
SUBF
ADDF
MPYF
—
n+2 RDY
SUBF
(nop)
ADDF
MPYF
n+3
ADDI
SUBF
(nop)
ADDF
Note:
PC = program counter
8.2.3.3
Execute Only
The execute-only type of memory pipeline conflict occurs when performing an
interlocked load or when a sequence of instructions requires three CPU data
accesses in a single cycle. There are two cases in which this occurs:
interlocked load or when a sequence of instructions requires three CPU data
accesses in a single cycle. There are two cases in which this occurs:
-
An instruction performs a store and is followed by an instruction that
performs two memory reads.
performs two memory reads.
-
An instruction performs two stores and is followed by an instruction that
performs at least one memory read.
performs at least one memory read.
-
An interlocked load (LDII or LDFI) instruction is performed, and XF1 = 1.
The first case is shown in Example 8–8. Since this sequence requires three
data memory accesses and only two are available, only the execute phase of
the pipeline is allowed to proceed. The dual reads required by the LDF || LDF
are delayed one cycle. In this case, a refetch of the next instruction can occur.
data memory accesses and only two are available, only the execute phase of
the pipeline is allowed to proceed. The dual reads required by the LDF || LDF
are delayed one cycle. In this case, a refetch of the next instruction can occur.