Texas Instruments TMS320C3x Manuale Utente
Read must wait
until the writes are
completed
until the writes are
completed
Writes
performed
performed
Pipeline Conflicts
8-14
Example 8–9 shows a parallel store followed by a single load or read. Since
two parallel stores are required, the next CPU data-memory read must wait
one cycle before beginning. One program-memory refetch can occur.
two parallel stores are required, the next CPU data-memory read must wait
one cycle before beginning. One program-memory refetch can occur.
Example 8–9. Parallel Store Followed by Single Read
STF
R0,*AR0
;
R0
→
*AR0 in parallel with
STF
R2,*AR1
;
R2
→
*AR1
ADDF
@SUM,R1
;
R1 + @SUM
→
R1
IACK
ASH
ASH
Pipeline Operation
PC
Fetch
Decode
Read
Execute
n
STF
STF
—
—
—
n+1
ADDF
STF
STF
—
—
n+2
IACK
ADDF
STF
STF
—
n+3
ASH
IACK
ADDF
STF
STF
n+4
ASH
IACK
ADDF
(nop)
n+4
—
ASH
IACK
ADDF
The final case involves an interlocked load (LDII or LDFI) instruction and XF1 = 1.
Since the interlocked loads use the XF1 pin as an acknowledge that the read
can complete, the loads might need to extend the read cycle, as shown in
Example 8–10. A program refetch can occur.
Since the interlocked loads use the XF1 pin as an acknowledge that the read
can complete, the loads might need to extend the read cycle, as shown in
Example 8–10. A program refetch can occur.