Texas Instruments TMS320C3x Manuale Utente

Parallel MPYI3 and SUBI3

13-170

 

This instruction’s operands have been augmented in the following 
devices:

-

’C31 silicon version 6.0 or greater

-

’C32 silicon version 2.0 or greater

srcA, srcB, srcC, srcD can be one of the following combinations:

v

v

2

2

–

2

1

1

2

–

2

dst1

register (

d1):

0 = R0
1 = R1

dst2

register (

d2):

0 = R2
1 = R3

src1

register (R

n, 0 

≤

n 

≤

 7)

src2

register (R

n, 0 

≤

 

n 

≤

 7)

src3

indirect (

disp = 0, 1, IR0, IR1) or any CPU register

src4

indirect (

disp = 0, 1, IR0, IR1) or any CPU register

P

parallel addressing modes (0 

≤

 P 

≤

 3)

Version 4.7 or earlier of TMS320 floating-point code-generation tools

P

srcA

srcB srcD

srcC

00

src4

×

src3, src1 + src2

01

src3

×

src1, src4 + src2

10

src1

×

src2, src4 + src4

11

src3

×

src1, src2 + src4