Texas Instruments TMS320C3x Manuale Utente

 Parallel MPYI3 and SUBI3

13-171

  Assembly Language Instructions

Version 5.0 or later

P

srcA

srcB srcD

srcC

00

src3

×

src4, src1 + src2

01

src3

×

src1, src4 + src2

10

src1

×

src2, src3 + src4

11

src3

×

src1, src2 + src4

31

24 23

16

8 7

0

15

1 0 0 0 1 1

P

src

4

src

3

src

1

src

2

d1 d2

An integer multiplication and an integer subtraction are performed in parallel.
All registers are read at the beginning and loaded at the end of the execute
cycle. If one of the parallel operations (MPYI3) reads from a register and the
operation being performed in parallel (SUBI3) writes to the same register,
MPYI3 accepts the contents of the register as input before it is modified by the
SUBI3.

Any combination of addressing modes can be coded for the four possible
source operands as long as two are coded as indirect and two are coded as reg-
ister. The assignment of the source operands 

srcA – srcD to the  src1 – src4

fields varies, depending on the combination of addressing modes used, and the
P field is encoded accordingly. To simplify processing when the order is not sig-
nificant, the assembler may change the order of operands in commutative op-
erations.

Integer overflow occurs when any of the 16 MSBs of the 48-bit result differs
from the MSB of the 32-bit output value.

1 (see 

Note: Cycle Count on page 13–173)

These condition flags are modified only if the destination register is R7 – R0.

Unaffected

1 if an integer overflow occurs; unchanged otherwise

1 if an integer underflow occurs; 0 otherwise

0

0

1 if an integer overflow occurs; 0 otherwise

Unaffected

Operation is affected by OVM bit value.

MPYI3

R2,*++AR0(1),R0

||

SUBI3

*AR5

– –

(IR1),R4,R2