Motorola MC68VZ328 Manuale Utente
9-2
MC68VZ328 User’s Manual
Interrupt Processing
9.1
Interrupt Processing
Interrupts on the MC68VZ328 are processed as illustrated in the flowchart shown in Figure 9-1. Details on
each stage of the flow diagram are as follows:
each stage of the flow diagram are as follows:
1. The interrupt controller collects interrupt events from both on- and off-chip peripherals.
Next, it prioritizes them and presents the highest priority request to the CPU if there are no
higher interrupts pending; otherwise, the highest priority interrupt is served first.
higher interrupts pending; otherwise, the highest priority interrupt is served first.
2. The CPU responds to the interrupt request by executing an interrupt acknowledge bus cycle
after the completion of the current instruction.
3. The interrupt controller recognizes the interrupt acknowledge (IACK) cycle and places the
interrupt vector for that interrupt request onto the CPU bus.
4. The CPU reads the vector and address of the interrupt handler in the exception vector table
and begins execution at that address.
Figure 9-1. Interrupt Processing Flowchart
Steps 2 and 4 are the responsibility of the CPU, whereas steps 1 and 3 are the responsibility of the interrupt
controller. External devices must not respond to IACK cycles with a vector because the response is solely
the responsibility of the interrupt controller.
controller. External devices must not respond to IACK cycles with a vector because the response is solely
the responsibility of the interrupt controller.
On the MC68VZ328, steps 2 and 4 operate exactly as they would on other M68000 devices, which are
described in the M68000 User’s Manual. In step 2, the CPU’s status register (SR) is available to mask
interrupts globally to determine which priority levels can currently generate interrupts. Also in step 2, the
interrupt acknowledge cycle is executed.
described in the M68000 User’s Manual. In step 2, the CPU’s status register (SR) is available to mask
interrupts globally to determine which priority levels can currently generate interrupts. Also in step 2, the
interrupt acknowledge cycle is executed.
In step 4, the CPU reads the vector number, multiplies it by four to get the vector address, fetches a 4-byte
program address from that vector address, and then jumps to that 4-byte address. This 4-byte address is the
location of the first instruction in the interrupt handler.
program address from that vector address, and then jumps to that 4-byte address. This 4-byte address is the
location of the first instruction in the interrupt handler.
The interrupt priority is based on the interrupt level. The interrupts with the same interrupt level are
prioritized by the software during the execution of the interrupt service routine. The MC68VZ328 provides
one interrupt vector for each interrupt level. The most significant 5 bits of the interrupt vector are
prioritized by the software during the execution of the interrupt service routine. The MC68VZ328 provides
one interrupt vector for each interrupt level. The most significant 5 bits of the interrupt vector are
Higher Interrupt
?
Yes
No
FLX68000 CPU
External or Internal
Interrupt
Interrupt Controller
Prioritizes Interrupt
Process Interrupt
Interrupt Handler
1
2
3
0xFFF...
4