Motorola MC68VZ328 Manuale Utente
9-4
MC68VZ328 User’s Manual
Reset
NOTE:
The MC68VZ328 does not provide autovector interrupts. At system
startup, the user interrupt vector must be programmed, thereby allowing
the processor to handle interrupts properly.
startup, the user interrupt vector must be programmed, thereby allowing
the processor to handle interrupts properly.
9.3
Reset
The reset exception corresponds to the highest exception level. A reset exception is processed for system
initialization and to recover from a catastrophic failure. Any processing that is in progress at the time of the
reset is aborted and cannot be recovered. Neither the program counter nor the status register is saved. The
processor is forced into the supervisor state. The interrupt priority mask is set at level 7. The address in the
first two words of the reset exception vector is fetched by the processor as the initial SSP (supervisor stack
pointer), and the address in the next two words of the reset exception vector is fetched as the initial
program counter.
initialization and to recover from a catastrophic failure. Any processing that is in progress at the time of the
reset is aborted and cannot be recovered. Neither the program counter nor the status register is saved. The
processor is forced into the supervisor state. The interrupt priority mask is set at level 7. The address in the
first two words of the reset exception vector is fetched by the processor as the initial SSP (supervisor stack
pointer), and the address in the next two words of the reset exception vector is fetched as the initial
program counter.
At startup or reset, the default chip-select (CSA0) is asserted and all other chip-selects are negated. The
CSA0 signal should be used to decode an EPROM/ROM memory space. In this case, the first two long
words of the EPROM/ROM memory space should be programmed to contain the initial SSP and PC. The
initial SSP should point to a RAM space, and the initial PC should point to the startup code within the
EPROM/ROM space so that the processor can execute the startup code to bring up the system.
CSA0 signal should be used to decode an EPROM/ROM memory space. In this case, the first two long
words of the EPROM/ROM memory space should be programmed to contain the initial SSP and PC. The
initial SSP should point to a RAM space, and the initial PC should point to the startup code within the
EPROM/ROM space so that the processor can execute the startup code to bring up the system.
1A
26
104
068
SD
Level 2 interrupt autovector
1B
27
108
06C
SD
Level 3 interrupt autovector
1C
28
112
070
SD
Level 4 interrupt autovector
1D
29
116
074
SD
Level 5 interrupt autovector
1E
30
120
078
SD
Level 6 interrupt autovector
1F
31
124
07C
SD
Level 7 interrupt autovector
20–2F
32–47
128–188
080–0BC
SD
TRAP instruction vectors
5
30–3F
48–63
192–255
0C0–0FF
SD
Unassigned, reserved
3
40–FF
64–255
256–1020
100–3FC
SD
User interrupt vectors
1.SP denotes supervisor program space and SD denotes supervisor data space.
2.Reset vector 0 requires four words, unlike the other vectors which only require two words, and it is located
in the supervisor program space.
in the supervisor program space.
3.Vector numbers 12–14, 16–23, and 48–63 are reserved for future enhancements by Motorola. No peripheral
devices should be assigned to these numbers.
devices should be assigned to these numbers.
4.The spurious interrupt vector is taken when there is a bus error indication during interrupt processing.
5.TRAP #n uses vector number 32 + n (decimal).
Table 9-1. Exception Vector Assignment (Continued)
Vector Number
Address Number
Space
1
Assignment
Hex
Decimal
Decimal
Hex