HP A2Y15AV Manuale Utente

100

Datasheet, Volume 2

This register, in conjunction with the corresponding Upper Limit Address register, 
controls the processor to PCI Express-G prefetchable memory access routing based on 
the following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits 
A[31:20] of the 40-bit address. The lower 8 bits of the Upper Limit Address register are 
read/write and correspond to address bits A[39:32] of the 40-bit address. This register 
must be initialized by the configuration software. For the purpose of address decode, 
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory 
address range will be at the top of a 1 MB aligned memory block. 

Prefetchable memory range is supported to allow segregation by the configuration 

software between the memory ranges that must be defined as UC and the ones that 

can be designated as a USWC (that is, prefetchable) from the processor perspective.

The functionality associated with this register is present in the PEG design 
implementation. This register in conjunction with the corresponding Upper Base 
Address register controls the processor to PCI Express-G prefetchable memory access 
routing based on the following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits 
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Base Address register are 
read/write and correspond to address bits A[38:32] of the 39-bit address. This register 
must be initialized by the configuration software. For the purpose of address decode, 
address bits A[19:0] are assumed to be 0. Thus, the bottom of the defined memory 
address range will be aligned to a 1 MB boundary.

15:4

RW

000h

Uncore

Prefetchable Memory Address Limit (PMLIMIT) 
This field corresponds to A[31:20] of the upper limit of the 

address range passed to PCI Express* graphics. 

3:0

RO

1h

Uncore

64-bit Address Support (AS64B)
This field indicates that the upper 32 bits of the prefetchable 

memory region limit address are contained in the Prefetchable 

Memory Base Limit Address register at 2Ch.

31:0

RW

0000000

0h

Uncore

Prefetchable Memory Base Address (PMBASEU)
This field corresponds to A[63:32] of the lower limit of the 

prefetchable memory range that will be passed to PCI Express-G.