HP A2Y15AV Manuale Utente

Datasheet, Volume 2

101

Processor Configuration Registers 

The functionality associated with this register is present in the PEG design 
implementation.

This register in conjunction with the corresponding Upper Limit Address register 
controls the processor to PCI Express-G prefetchable memory access routing based on 
the following formula:

PREFETCHABLE_MEMORY_BASE ≤ address ≤ PREFETCHABLE_MEMORY_LIMIT

The upper 12 bits of this register are read/write and correspond to address bits 
A[31:20] of the 39-bit address. The lower 7 bits of the Upper Limit Address register are 
read/write and correspond to address bits A[38:32] of the 39-bit address. This register 
must be initialized by the configuration software. For the purpose of address decode, 
address bits A[19:0] are assumed to be FFFFFh. Thus, the top of the defined memory 
address range will be at the top of a 1 MB aligned memory block. 

Prefetchable memory range is supported to allow segregation by the configuration 

software between the memory ranges that must be defined as UC and the ones that 

can be designated as a USWC (that is, prefetchable) from the processor perspective.

The capabilities pointer provides the address offset to the location of the first entry in 
this device's linked list of capabilities.

31:0

RW

00000000h

Uncore

Prefetchable Memory Address Limit (PMLIMITU)
This field corresponds to A[63:32] of the upper limit of the 

prefetchable Memory range that will be passed to PCI Express-

G. 

7:0

RO

88h

Uncore

First Capability (CAPPTR1)
The first capability in the list is the Subsystem ID and Subsystem 

Vendor ID Capability.