HP A2Y15AV Manuale Utente

146

Datasheet, Volume 2

Lane Equalization Control Register (2 lanes are combined, lane "0" is the lower 
numbered lane, lane "1" is the higher numbered lane).

31:26

RW

3Eh

Uncore

Full Swing Value (FS) 
FS is used to calculate the transmitter coefficients during 

Equalization. Default is 62d. 

Note: all equalization presets’ coefficients have been calculated 

using the default FS value of 62d. If FS is changed, the preset 

tables located in EQPRESET* registers may need to be re-

programmed to fulfill FS. 
FS = |Cm1| + C0 + |Cp1| 
(C0 > 0)

25:20

RW

14h

Uncore

Low Frequency Value (LF) 
LF is used to calculate the transmitter coefficients during 

Equalization. Default is 20d.
Note: All equalization presets’ coefficients have been calculated 

using the default LF value of 20d. If LF is changed, the preset 

tables located in EQPRESET* registers may need to be re-

programmed to fulfill LF. 
Cm1 + C0 + Cp1 > LF

19:16

RO

0h

15

RW

0b

Uncore

Bypass Phase 2 Equalization (EQPH2BYP) 
If set, after Phase 1 is complete, the LTSSM will bypass Phase 2 

and 3 of equalization.

14

RW

1b

Uncore

Bypass Phase 3 Equalization (EQPH3BYP) 
If set, after Phase 2 is complete, the LTSSM will bypass Phase 3 

of equalization and go back to Recovery.RcvrLock.

13

RW

0b

Uncore

Disable Margining (MARGINDIS) 
When set, it will disable Tx margining during Polling.Compliance 

and Recovery.

12:8

RO

0h

7

RW

0b

Uncore

Gen3 Bypass Levels (G3BYPLVL) 
If this bit is set, the Tx Eq Levels will be bypassed only during 

Gen3. The values of the bypass levels are found in the port 

EQBYPLVLBND* registers.
When this bit is set, Phase 2 and Phase 3 equalization is expected 

to be bypassed.

6

RW

0b

Uncore

Global Bypass Levels (GLBBYPLVL) 
If this bit is set, the Tx Eq Levels will be bypassed for all speeds. 

The values of the bypass levels are found in the port 

EQBYPLVLBND* registers.
When this bit is set, Phase 2 and Phase 3 equalization is expected 

to be bypassed.