HP A2Y15AV Manuale Utente

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Processor Configuration Registers
148
Datasheet, Volume 2
2.8
PCI Device 2 Configuration Space
 Registers
Table 2-11. PCI Device 2 Configuration Space Register Address Map 
Address 
Offset
Register 
Symbol
Register Name
Reset Value
Access
0–1h
VID2
Vendor Identification
8086h
RO
2–3h
DID2
Device Identification
0152h
RO-V, RO-FW
4–5h
PCICMD2
PCI Command
0000h
RW, RO
6–7h
PCISTS2
PCI Status
0090h
RO, RO-V
8h
RID2
Revision Identification
00h
RO-FW
9–Bh
CC
Class Code
030000h
RO-V, RO
Ch
CLS
Cache Line Size
00h
RO
Dh
MLT2
Master Latency Timer
00h
RO
Eh
HDR2
Header Type
00h
RO
Fh
RSVD
Reserved
0h
RO
10–17h
GTTMMADR
Graphics Translation Table, Memory 
Mapped Range Address
000000000
0000004h
RO, RW
18–1Fh
GMADR
Graphics Memory Range Address
00000000
0000000Ch
RW, RO, 
RW-L
20–23h
IOBAR
I/O Base Address
00000001h
RW, RO
24–2Bh
RSVD
Reserved
0h
RO
2C–2Dh
SVID2
Subsystem Vendor Identification
0000h
RW-O
2E–2Fh
SID2
Subsystem Identification
0000h
RW-O
30–33h
ROMADR
Video BIOS ROM Base Address
00000000h
RO
34h
CAPPOINT
Capabilities Pointer
90h
RO-V
35–3Bh
RSVD
Reserved
0h
RO
3Ch
INTRLINE
Interrupt Line
00h
RW
3Dh
INTRPIN
Interrupt Pin
01h
RO
3Eh
MINGNT
Minimum Grant
00h
RO
3Fh
MAXLAT
Maximum Latency
00h
RO
40–61h
RSVD
Reserved
 —
62h
MSAC
Multi Size Aperture Control
02h
RW, RW-K
63–FFh
RSVD
Reserved