HP A2Y15AV Manuale Utente

Datasheet, Volume 2

167

Processor Configuration Registers 

This register contains the revision number of the processor root port. These bits are 
read only and writes to this register have no effect.

8

RW1C

0b

Uncore

Master Data Parity Error (PMDPE)
This bit is set by a Requester (Primary Side for Type 1 

Configuration Space header Function) if the Parity Error Response 

bit in the Command register is 1b and either of the following two 

conditions occurs:
• Requester receives a Completion marked poisoned
• Requester poisons a write Request
If the Parity Error Response bit is 0b, this bit is never set.
Reset Value of this bit is 0b.
This bit will be set only for completions of requests encountering 

ECC error in DRAM.
Poisoned peer-2-peer posted forwarded will not set this bit. They 

are reported at the receiving port.

7

RO

0b

Uncore

Fast Back-to-Back (FB2B)
Not Applicable or Implemented. Hardwired to 0. 

6

RO

0h

5

RO

0b

Uncore

66/60MHz capability (CAP66)
Not Applicable or Implemented. Hardwired to 0. 

4

RO

1b

Uncore

Capabilities List (CAPL)
Indicates that a capabilities list is present. Hardwired to 1. 

3

RO-V

0b

Uncore

INTx Status (INTAS)
This bit indicates that an interrupt message is pending internally 

to the device. Only PME and Hot-plug sources feed into this 

status bit (not PCI INTA–INTD assert and deassert messages). 

The INTA Assertion Disable bit, PCICMD1[10], has no effect on 

this bit.
INTA emulation interrupts received across the link are not 

reflected in this bit. 
Note: PCI Express* Hot-Plug is not supported on the processor. 

2:0

RO

0h

7:0

RO-FW

0h

Uncore

Revision Identification Number (RID)
This is an 8-bit value that indicates the revision identification 

number for the root port. Refer to the Mobile 3rd Generation 

 Core™ Processor Family Specification Update for the value 

of the RID register.