HP A2Y15AV Manuale Utente

Datasheet, Volume 2

169

Processor Configuration Registers 

This register identifies that this "virtual" Host-PCI Express* bridge is connected to PCI 
bus 0.

This register identifies the bus number assigned to the second bus side of the "virtual" 
bridge; that is, to PCI Express-G. This number is programmed by the PCI configuration 
software to allow mapping of configuration cycles to PCI Express-G.

This register identifies the subordinate bus (if any) that resides at the level below PCI 
Express-G. This number is programmed by the PCI configuration software to allow 
mapping of configuration cycles to PCI Express-G.

7:0

RO

00h

Uncore

Primary Bus Number (BUSN) 
Configuration software typically programs this field with the 

number of the bus on the primary side of the bridge. Since the 

processor root port is an internal device and its primary bus is 

always 0, these bits are read only and are hardwired to 0. 

7:0

RW

00h

Uncore

Secondary Bus Number (BUSN)
This field is programmed by configuration software with the bus 

number assigned to PCI Express-G. 

7:0

RW

00h

Uncore

Subordinate Bus Number (BUSN)
This register is programmed by configuration software with the 

number of the highest subordinate bus that lies behind the 

processor root port bridge. When only a single PCI device resides 

on the PCI Express-G segment, this register will contain the same 

value as the SBUSN1 register.