HP A2Y15AV Manuale Utente
Datasheet, Volume 2
21
Processor Configuration Registers
Compatible SMRAM Address Range (A_0000h–B_FFFFh)
When compatible SMM space is enabled, SMM-mode processor accesses to this range
route to physical system DRAM at 000A_0000h–000B_FFFFh.
route to physical system DRAM at 000A_0000h–000B_FFFFh.
PCI Express and DMI originated cycles to enable SMM space are not allowed and are
considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI
initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port.
considered to be to the Video Buffer Area, if IGD is not enabled as the VGA device. DMI
initiated writes cycles are attempted as peer writes cycles to a VGA enabled PCIe port.
Monochrome Adapter (MDA) Range (B_0000h–B_7FFFh)
Legacy support requires the ability to have a second graphics controller (monochrome)
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express,
or the DMI Interface (depending on configuration bits). Since the monochrome adapter
may be mapped to any of these devices, the processor must decode cycles in the MDA
range (000B_0000h–000B_7FFFh) and forward either to IGD, PCI Express, or the DMI
Interface. This capability is controlled by the VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the
processor decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards
them to the either IGD, PCI Express, and/or the DMI Interface.
in the system. Accesses in the standard VGA range are forwarded to IGD, PCI Express,
or the DMI Interface (depending on configuration bits). Since the monochrome adapter
may be mapped to any of these devices, the processor must decode cycles in the MDA
range (000B_0000h–000B_7FFFh) and forward either to IGD, PCI Express, or the DMI
Interface. This capability is controlled by the VGA steering bits and the legacy
configuration bit (MDAP bit). In addition to the memory range B0000h to B7FFFh, the
processor decodes I/O cycles at 3B4h, 3B5h, 3B8h, 3B9h, 3BAh and 3BFh and forwards
them to the either IGD, PCI Express, and/or the DMI Interface.
PEG 16-bit VGA Decode
The PCI to PCI Bridge Architecture Specification Revision 1.2, it is required that 16-bit
VGA decode be a feature.
VGA decode be a feature.
When 16-bit VGA decode is disabled, the decode of VGA I/O addresses is performed on
10 lower bits only, essentially mapping also the aliases of the defined I/O addresses.
10 lower bits only, essentially mapping also the aliases of the defined I/O addresses.
2.3.1.3
PAM (C_0000h–F_FFFFh)
The 13 sections from 768 KB to 1 MB comprise what is also known as the PAM Memory
Area. Each section has Read enable and Write enable attributes.
Area. Each section has Read enable and Write enable attributes.
The PAM registers are mapped in Device 0 configuration space.
• ISA Expansion Area (C_0000h–D_FFFFh)
• Extended System BIOS Area (E_0000h–E_FFFFh)
• System BIOS Area (F_0000h–F_FFFFh)
• Extended System BIOS Area (E_0000h–E_FFFFh)
• System BIOS Area (F_0000h–F_FFFFh)
The processor decodes the core request; then routes to the appropriate destination
(DRAM or DMI).
(DRAM or DMI).
Snooped accesses from PCI Express or DMI to this region are snooped on processor
caches.
caches.
Non-snooped accesses from PCI Express or DMI to this region are always sent to
DRAM.
DRAM.
Graphics translated requests to this region are not allowed. If such a mapping error
occurs, the request will be routed to C_0000. Writes will have the byte enables de-
asserted.
occurs, the request will be routed to C_0000. Writes will have the byte enables de-
asserted.