HP A2Y15AV Manuale Utente
Processor Configuration Registers
22
Datasheet, Volume 2
2.3.2
Main Memory Address Range (1 MB – TOLUD)
This address range extends from 1 MB to the top of Low Usable physical memory that is
permitted to be accessible by the processor (as programmed in the TOLUD register).
The processor will route all addresses within this range to the DRAM unless it falls into
the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
permitted to be accessible by the processor (as programmed in the TOLUD register).
The processor will route all addresses within this range to the DRAM unless it falls into
the optional TSEG, optional ISA Hole, or optional IGD stolen VGA memory.
2.3.2.1
ISA Hole (15 MB – 16 MB)
The ISA Hole is enabled in the Legacy Access Control Register in Device 0 configuration
space. If no hole is created, the processor will route the request to DRAM. If a hole is
created, the processor will route the request to DMI, since the request does not target
DRAM.
space. If no hole is created, the processor will route the request to DRAM. If a hole is
created, the processor will route the request to DMI, since the request does not target
DRAM.
Graphics translated requests to the range will always route to DRAM.
Figure 2-3. Main Memory Address Range
Main Memory
ISA Hole (optional)
DOS Compatibility Memory
0h
FLASH
FFFF_FFFFh
00F0_0000h
15MB
16MB
0100_0000h
0MB
TOLUD
APIC
Main Memory
0010_0000h
1MB
IGD
Intel
®
TXT
PCI Memory Range
4 GB Max
Contains:
Dev 0, 1, 2, 6, 7
BARS & PCH/PCI
ranges
Dev 0, 1, 2, 6, 7
BARS & PCH/PCI
ranges
TSEG
IGGTT
DPR
TSEG_BASE