HP A2Y15AV Manuale Utente

250

Datasheet, Volume 2

Thie register provides refresh timing parameters.

Thie register provides self-refresh timing parameters.

31:25

RW-L

23h

Uncore

9 * tREFI (tREFIx9) 
Period of minimum between 9*tREFI and tRAS maximum 

(normally 70 us) in 1024 * DCLK cycles (default is 35h) – need to 

reduce 100 DCLK cycles – uncertainty on timing of panic refresh 

24:16

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0B4h

Uncore

Refresh Execution Time (tRFC) 
Time of refresh – from beginning of refresh until next ACT or 

refresh is allowed (in DCLK cycles, default is 180h) 

15:0

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1004h

Uncore

tREFI Period in DCLK Cycles (tREFI) 
Defines the average period between refreshes, and the rate that 

tREFI counter is incremented (in DCLK cycles, default is 4100h) 

31:28

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0h

Uncore

(tMOD) 
The time between MRS command and any other command in 

DCLK cycles.
Actual value is 8 + programmed-Value. For example when 

programming 4 in the field, tMOD value is actually 12 DCLK 

cycles. 

27:26

RO

0h

25:16

RW-L

100h

Uncore

(tZQOPER) 
This field defines the period required for ZQCL after SR exit. 

15:12

RW-L

Bh

Uncore

(tXS_offset) 
Delay from SR exit to the first DDR command.
tXS = tRFC+10ns. Setup of tXS_offset is # of cycles for 10 ns. 

The range is between 3 and 11 DCLK cycles.

11:0

RW-L

200h

Uncore

(tXSDLL) 
Delay between DDR SR exit and the first command that requires 

data RD/WR from DDR is in the range of 128 to 1024 DCLK 

cycles, though all JEDEC DDRs assume 512 DCLK cycles.