HP A2Y15AV Manuale Utente

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Datasheet, Volume 2
251
Processor Configuration Registers 
2.15
MCHBAR Registers in Memory Controller – 
Integrated Memory Peripheral Hub (IMPH)
2.15.1
CRDTCTL3—Credit Control 3 Register
This register will have the minimum Read Return Tracker credits for each of the 
PEG/DMI/GSA streams.
Table 2-18. MCHBAR Registers in Memory Controller –Integrated Memory Peripheral  
Hub (IMPH) Register Address Map 
Address 
Offset
Register Symbol
Register Name
Reset Value
Access
0–740Bh
RSVD
Reserved
740C–740Fh
CRDTCTL3
Credit Control 3
B124F851h
RW-L
7410–7413h
CRDTCTL4
Credit Control 4
00000017h
RW-L
7410C–7FFFh
RSVD
Reserved
B/D/F/Type: 0/0/0/MCHBAR IMPH
Address Offset:
740C–740Fh
Reset Value:
B124F851h
Access:
RW-L
Size:
32 bits
Bit
Access
Reset 
Value
RST/
PWR
Description
31:27
RW-L
16h
Uncore
GSA VC1 Minimum Completion Credits (GSAVC1) 
Minimum number of credits for GSA VC1 completions 
26:24
RW-L
1h
Uncore
GSA VC0 Minimum Completion Credits (GSAVC0) 
Minimum number of credits for GSA VC0 completions 
23:21
RW-L
1h
Uncore
PEG60 VC0 Minimum Completion Credits (PEG60VC0) 
Minimum number of credits for PEG60 VC0 completions 
20:18
RW-L
1h
Uncore
PEG12 VC0 Minimum Completion Credits (PEG12VC0) 
Minimum number of credits for PEG12 VC0 completions 
17:15
RW-L
1h
Uncore
PEG11 VC0 Minimum Completion Credits (PEG11VC0) 
Minimum number of credits for PEG11 VC0 completions 
14:12
RW-L
7h
Uncore
PEG10 VC0 Minimum Completion Credits (PEG10VC0) 
Minimum number of credits for PEG10 VC0 completions 
11:9
RW-L
4h
Uncore
DMI VC1 Minimum Completion Credits (DMIVC1) 
Minimum number of credits for DMI VC1 completions
8:6
RW-L
1h
Uncore
DMI VCm Minimum Completion Credits (DMIVCM) 
Minimum number of credits for DMI VCm completions 
5:3
RW-L
2h
Uncore
DMI VCp Minimum Completion Credits (DMIVCP) 
Minimum number of credits for DMI VCp completions 
2:0
RW-L
1h
Uncore
DMI VC0 Minimum Completion Credits (DMIVC0) 
Minimum number of credits for DMI VC0 completions