HP A2Y15AV Manuale Utente
Datasheet, Volume 2
35
Processor Configuration Registers
2.3.5
PCI Express* Configuration Address Space
PCIEXBAR is located in Device 0 configuration space. The processor detects memory
accesses targeting PCIEXBAR. BIOS must assign this address range such that it will not
conflict with any other address ranges.
accesses targeting PCIEXBAR. BIOS must assign this address range such that it will not
conflict with any other address ranges.
See the configuration portion of this document for more details.
2.3.6
PCI Express* Graphics Attach (PEG)
The processor can be programmed to direct memory accesses to a PCI Express
interface. When addresses are within either of two ranges specified using registers in
each PEG(s) configuration space.
interface. When addresses are within either of two ranges specified using registers in
each PEG(s) configuration space.
• The first range is controlled using the Memory Base (MBASE) register and Memory
Limit (MLIMIT) register.
• The second range is controlled using the Pre-fetchable Memory Base (PMBASE)
register and Pre-fetchable Memory Limit (PMLIMIT) register.
Conceptually, address decoding for each range follows the same basic concept. The top
12 bits of the respective Memory Base and Memory Limit registers correspond to
address bits A[31:20] of a memory address. For the purpose of address decoding, the
processor assumes that address bits A[19:0] of the memory base are zero and that
address bits A[19:0] of the memory limit address are F_FFFFh. This forces each
memory address range to be aligned to 1 MB boundary and to have a size granularity
of 1 MB.
12 bits of the respective Memory Base and Memory Limit registers correspond to
address bits A[31:20] of a memory address. For the purpose of address decoding, the
processor assumes that address bits A[19:0] of the memory base are zero and that
address bits A[19:0] of the memory limit address are F_FFFFh. This forces each
memory address range to be aligned to 1 MB boundary and to have a size granularity
of 1 MB.
The processor positively decodes memory accesses to PCI Express memory address
space as defined by the following equations:
space as defined by the following equations:
Memory_Base_Address ≤ Address ≤ Memory_Limit_Address
Prefetchable_Memory_Base_Address ≤ Address ≤
Prefetchable_Memory_Limit_Address
The window size is programmed by the plug-and-play configuration software. The
window size depends on the size of memory claimed by the PCI Express device.
Normally, these ranges will reside above the Top-of-Low Usable-DRAM and below High
BIOS and APIC address ranges. They MUST reside above the top of low memory
(TOLUD) if they reside below 4 GB and MUST reside above top of upper memory
(TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space.
window size depends on the size of memory claimed by the PCI Express device.
Normally, these ranges will reside above the Top-of-Low Usable-DRAM and below High
BIOS and APIC address ranges. They MUST reside above the top of low memory
(TOLUD) if they reside below 4 GB and MUST reside above top of upper memory
(TOUUD) if they reside above 4 GB or they will steal physical DRAM memory space.
It is essential to support a separate Pre-fetchable range in order to apply USWC
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
attribute (from the processor point of view) to that range. The USWC attribute is used
by the processor for write combining.
Note:
The processor memory range registers described above are used to allocate memory
address space for any PCI Express devices sitting on PCI Express that require such a
window.
The PCICMD register can override the routing of memory accesses to PCI Express. In
other words, the memory access enable bit must be set to enable the memory
base/limit and pre-fetchable base/limit windows.
other words, the memory access enable bit must be set to enable the memory
base/limit and pre-fetchable base/limit windows.
The upper PMUBASE/PMULIMIT registers are implemented for PCI Express Specification
compliance. The processor locates MMIO space above 4 GB using these registers.
compliance. The processor locates MMIO space above 4 GB using these registers.