HP A2Y15AV Manuale Utente

60

Datasheet, Volume 2

This is the base address for the PCI Express configuration space. This window of 
addresses contains the 4 KB of configuration space for each PCI Express device that 
can potentially be part of the PCI Express Hierarchy associated with the Uncore. There 
is no actual physical memory within this window of up to 256 MB that can be 
addressed. The actual size of this range is determined by a field in this register.

Each PCI Express Hierarchy requires a PCI Express BASE register. The Uncore supports 
one PCI Express Hierarchy. The region reserved by this register does not alias to any 
PCI2.3 compliant memory mapped space. For example, the range reserved for 
MCHBAR is outside of PCIEXBAR space.

On reset, this register is disabled and must be enabled by writing a 1 to the enable field 
in this register. This base address shall be assigned on a boundary consistent with the 
number of buses (defined by the length field in this register), above TOLUD and still 
within 39-bit addressable memory space.

The PCI Express Base Address cannot be less than the maximum address written to the 
Top of physical memory register (TOLUD). Software must ensure that these ranges do 
not overlap with known ranges located above TOLUD.

Software must ensure that the sum of the length of the enhanced configuration region 
+ TOLUD + any other known ranges reserved above TOLUD is not greater than the 39-
bit addessable limit of 512 GB. In general, system implementation and the number of 
PCI/PCI Express/PCI-X buses supported in the hierarchy will dictate the length of the 
region.

All the bits in this register are locked in Intel TXT mode.

63:39

RO

0h

38:28

RW

000h

Uncore

PCI Express* Base Address (PCIEXBAR) 
This field corresponds to bits 38:28 of the base address for PCI 

Express enhanced configuration space. BIOS will program this 

register resulting in a base address for a contiguous memory 

address space. The size of the range is defined by bits 2:1 of this 

register.
This Base address shall be assigned on a boundary consistent 

with the number of buses (defined by the Length field in this 

register) above TOLUD and still within the 39-bit addressable 

memory space. The address bits decoded depend on the length 

of the region defined by this register.
This register is locked by Intel TXT.
The address used to access the PCI Express configuration space 

for a specific device can be determined as follows:
PCI Express Base Address + Bus Number * 1MB + Device 

Number * 32 KB + Function Number * 4 KB
This address is the beginning of the 4 KB space that contains 

both the PCI compatible configuration space and the PCI Express 

extended configuration space.