HP A2Y15AV Manuale Utente
Datasheet, Volume 2
59
Processor Configuration Registers
2.5.15
PAVPC—Protected Audio Video Path Control Register
All the bits in this register are locked by Intel TXT. When locked, the RW bits are RO.
2.5.16
DPR—DMA Protected Range Register
DMA protected range register.
B/D/F/Type:
0/0/0/PCI
Address Offset:
58–5Bh
Reset Value:
00000000h
Access:
RW-L, RW-KL
Size:
32 bits
Bit
Access
Reset
Value
RST/
PWR
Description
31:3
RO
0h
Reserved (RSVD)
2
RW-KL
0b
Uncore
PAVP Lock (PAVPLCK)
This bit will lock all writeable contents in this register when set
This bit will lock all writeable contents in this register when set
(including itself). Only a hardware reset can unlock the register
again.
For the processor, this Lock bit needs to be set only if PAVP is
For the processor, this Lock bit needs to be set only if PAVP is
enabled (bit_PAVPE = '1`).
1:0
RO
0h
Reserved (RSVD)
B/D/F/Type:
0/0/0/PCI
Address Offset:
5C–5Fh
Reset Value:
00000000h
Access:
RW-L, RO-V, RW-KL
Size:
32 bits
BIOS Optimal Default
000h
Bit
Access
Reset
Value
RST/
PWR
Description
31:3
RO
0h
Reserved (RSVD)
2
RW-L
0b
Uncore
Enable Protected Memory (EPM)
This field controls DMA accesses to the DMA Protected Range
This field controls DMA accesses to the DMA Protected Range
(DPR) region.
0 = DPR is disabled
1 = DPR is enabled. All DMA requests accessing DPR region are
0 = DPR is disabled
1 = DPR is enabled. All DMA requests accessing DPR region are
blocked.
Hardware reports the status of DPR enable/disable through the
PRS field in this register.
1
RO-V
0b
Uncore
Protected Region Status (PRS)
This field indicates the status of DPR.
0 = DPR protection disabled
1 = DPR protection enabled
This field indicates the status of DPR.
0 = DPR protection disabled
1 = DPR protection enabled
0
RO
0h
Reserved (RSVD)