Samsung MZMPC128HBFU-00000 Manuale Utente

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datasheet

SSD

Rev. 1.0

MZMPC032HBCD-00000

MZMPC064HBDR-00000

MZMPC128HBFU-00000

MZMPC256HBGJ-00000

8.2 Phy Power State

8.2.1 COMRESET sequence state diagram

8.2.2 Interface Power States

8.2.2.1 PHYRDY

The Phy logic and main PLL are both on and active. The interface is
synchronized and capable of receiving and sending data.

8.2.2.2 Partial

The Phy logic is powered, but is in a reduced power state. Both signal lines on the interface are at a neutral logic state (common mode voltage). The exit
latency from this state shall be no longer than 10 us.

8.2.2.3 Slumber

The Phy logic is powered but is in a reduced power state. The exit latency from this state shall be no longer than 10 ms.

8.2.3 Partial/Slumber to PHYRDY

8.2.3.1 Host Initiated

The host may initiate a wakeup from the Partial or Slumber states by entering the power-on sequence at the “Host COMWAKE” point in the state
machine. Calibration and speed negotiation is bypassed since it has already been performed at power-on and system performance depends on quick
resume latency. The device, therefore, shall transmit ALIGNP primitives at the speed determined at power-on.

8.2.3.2 Device Initiated

The device may initiate a wakeup from the Partial or Slumber states by entering the power-on sequence at the “Device COMWAKE” point in the state
machine. Calibration and speed negotiation is bypassed since it has already been performed at power-on and system performance depends on quick
resume latency. The device, therefore, shall transmit ALIGNP primitives at the speed determined at power-on.