Intel E3-1105C AV8062701048800 Scheda Tecnica

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

May 2012

Datasheet - Volume 1 of 2

Document Number: 327405

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001

151

This section contains register information that is specific to the Intel

®

 Xeon

®

, Intel

®

 

Core™, Intel

®

 Pentium

®

 and Intel

®

 Celeron

®

 Processors for Communications 

Infrastructure. For other register details see the latest version of the 2nd Generation 

 Core™ Processor Family Mobile Datasheet – Volume 2.

The processor does not include the Integrated Display Engine or the Graphics Processor 

Unit (GPU). Disregard references to graphics and Intel

®

 Turbo Boost in the 2nd 

 Core™ Processor Family Mobile Datasheet – Volume 2.

 shows the register-related terminology that is used in this document.

 lists the modifiers used in conjunction with attributes that are included in 

the register tables throughout this document.

RO

Read Only: These bits can only be read by software, writes have no effect. The value of 

the bits is determined by the hardware only.

RW

Read/Write: These bits can be read and written by software.

RW1C

Read / Write 1 to Clear: These bits can be read and cleared by software. Writing a '1' to a 

bit will clear it, while writing a '0' to a bit has no effect. Hardware sets these bits.

RW0C

Read/Write 0 to Clear: These bits can be read and cleared by software. Writing a ‘0’ to a 

bit will clear it, while writing a ‘1’ to a bit has no effect. Hardware sets these bits.

RW1S

Read / Write 1 to Set: 

These bits can be read and set by software. Writing a ‘1’ to a bit will 

set it, while writing a ‘0’ to a bit has no effect. Hardware clears these bits.

RsvdP

Reserved and Preserved: 

These bits are reserved for future RW implementations and their 

value must not be modified by software. When writing to these bits, software must 

preserve the value read. When SW updates a register that has RsvdP fields, it must read 

the register value first so that the appropriate merge between the RsvdP and updated 

fields will occur.

RsvdZ

Reserved and Zero: 

These bits are reserved for future RW1C implementations. SW must 

use 0 for writes.

WO

Write Only: 

These bits can only be written by software, reads return zero. 

NOTE: Use of this attribute type is deprecated and can only be used to describe bits 

without persistent state.

RC

Read Clear: 

These bits can only be read by software, but a read causes the bits to be 

cleared. Hardware sets these bits. 
NOTE: Use of this attribute type is only allowed on legacy functions, as side-effects on 

reads are not desirable

RSW1C

Read Set / Write 1 to Clear: 

These bits can be read and cleared by software. Reading a bit will 

set the bit to ‘1’. Writing a ‘1’ to a bit will clear it, while writing a ‘0’ to a bit has no effect.

RCW

Read Clear / Write: 

These bits can be read and written by software, but a read causes the 

bits to be cleared. 
NOTE: Use of this attribute type is only allowed on legacy functions, as side-effects on 

reads are not desirable.