Intel E3-1105C AV8062701048800 Scheda Tecnica

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

152

Document Number: 327405

-

001

B/D/F/Type:

0/0/0/PCI

Address Offset:

C8-C9h

Default Value:

0000h

Access:

RO; RW1C-S 

Size:

16 bits

BIOS Optimal Default

0000h

This register is used to report various error conditions via the SERR DMI messaging 

mechanism. The SERR DMI message is generated on a zero to one transition of any of 

these flags (if enabled by the ERRCMD and PCICMD registers).

These bits are set regardless of whether or not the SERR is enabled and generated. 

After the error processing is complete, the error logging mechanism can be unlocked by 

clearing the appropriate status bit by software writing a '1' to it

.

S

RO (with -V)

Sticky: These bits are only re-initialized to their 

default value by a Power Good Reset. 
Note: Does not apply to RO (constant) bits.

RW

RW1C

RW1S

-K

RW

Key: These bits control the ability to write other bits 

(identified with a Lock modifier).

-L

RW

Lock: Hardware can make these bits Read-Only via a 

separate configuration bit or other logic. 
Note: Mutually exclusive with Once modifier.

WO

-O

RW

Once: After reset, these bits can only be rewritten by 

software once after which they become Read Only. 
Note: Mutually exclusive with Variant modifier

WO

-FW

RO

Firmware Write: The value of these bits can be 

updated by firmware (PCU, TAR, etc.).

-V

RO

Variant: The value of these bits can be updated by 

hardware. 
Note: RW1C and RC are variant by definition and 

therefore do not need to be modified.

15:2

RO

0h

Reserved (RSVD)