Intel E3-1105C AV8062701048800 Scheda Tecnica

Codici prodotto

AV8062701048800

Power Management

Intel

Xeon

and Intel

Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

Document Number: 327405

001

• A package C-state request is determined by the lowest numerical core C-state

amongst all cores.

• A package C-state is automatically resolved by the processor depending on the

core idle power states and the status of the platform components.

— Each core can be at a lower idle power state than the package if the platform

does not grant the processor permission to enter a requested package C-state.

— The platform may allow additional power savings to be realized in the

processor.

— For package C-states, the processor is not required to enter C0 before entering

any other C-state.

The processor exits a package C-state when a break event is detected. Depending on

the type of break event, the processor does the following:

• If a core break event is received, the target core is activated and the break event

message is forwarded to the target core.

— If the break event is not masked, the target core enters the core C0 state and

the processor enters package C0.

— If the break event is masked, the processor attempts to re-enter its previous

package state.

• If the break event was due to a memory access or snoop request.

— But the platform did not request to keep the processor in a higher package C-

state, the package returns to its previous C-state.

— And the platform requests a higher power C-state, the memory access or snoop

request is serviced and the package remains in the higher power C-state.

shows package C-state resolution for a dual-core processor.

summarizes package C-state transitions.

Table 6-9.

Coordination of Core Power States at the Package Level

Package

C-State

Core 1

Notes:

If enabled, the package C-state will be C1E if all actives cores have also resolved a core C1 state or

higher.