Intel E3-1105C AV8062701048800 Scheda Tecnica

Intel

®

 Xeon

®

 and Intel

®

 Core™ Processors For Communications Infrastructure

Datasheet - Volume 1 of 2

May 2012

56

Document Number: 327405

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001

A processor enters the package C3 low power state when:

• At least one core is in the C3 state.
• The other cores are in a C3 or lower power state, and the processor has been 

granted permission by the platform. 

• The platform has not granted a request to a package C6/C7 state but has allowed a 

package C6 state.

In package C3-state, the L3 shared cache is snoopable.

A processor enters the package C6 low power state when:

• At least one core is in the C6 state.
• The other cores are in a C6 or lower power state, and the processor has been 

granted permission by the platform.

• The platform has not granted a package C7 request but has allowed a C6 package 

state.

In package C6 state, all cores have saved their architectural state and have had their 

core voltages reduced to zero volts. The L3 shared cache is still powered and snoopable 

in this state. The processor remains in package C6 state as long as any part of the L3 

cache is active.

The processor enters the package C7 low power state when all cores are in the C7 state 

and the L3 cache is completely flushed. The last core to enter the C7 state begins to 

shrink the L3 cache by N-ways until the entire L3 cache has been emptied. This allows 

further power savings.

Core break events are handled the same way as in package C3 or C6. However, snoops 

are not sent to the processor in package C7 state because the platform, by granting the 

package C7 state, has acknowledged that the processor possesses no snoopable 

information. This allows the processor to remain in this low power state and maximize 

its power savings.

Upon exit of the package C7 state, the L3 cache is not immediately re-enabled. It 

re-enables once the processor has stayed out of the C6 or C7 for an preset amount of 

time. Power is saved since this prevents the L3 cache from being re-populated only to 

be immediately flushed again.

Upon entry into the package C7 state, the L3 cache is reduced by N-ways until it is 

completely flushed. The number of ways, N, is dynamically chosen per concurrent C7 

entry. Similarly, upon exit, the L3 cache is gradually expanded based on internal 

heuristics.